OpenCores
URL https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk

Subversion Repositories robust_axi_fabric

[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [def_ic_static.txt] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 eyalhoc
<##//////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  Author: Eyal Hochberg                                      ////
4
////          eyal@provartec.com                                 ////
5
////                                                             ////
6
////  Downloaded from: http://www.opencores.org                  ////
7
/////////////////////////////////////////////////////////////////////
8
////                                                             ////
9
//// Copyright (C) 2010 Provartec LTD                            ////
10
//// www.provartec.com                                           ////
11
//// info@provartec.com                                          ////
12
////                                                             ////
13
//// This source file may be used and distributed without        ////
14
//// restriction provided that this copyright statement is not   ////
15
//// removed from the file and that any derivative work contains ////
16
//// the original copyright notice and the associated disclaimer.////
17
////                                                             ////
18
//// This source file is free software; you can redistribute it  ////
19
//// and/or modify it under the terms of the GNU Lesser General  ////
20
//// Public License as published by the Free Software Foundation.////
21
////                                                             ////
22
//// This source is distributed in the hope that it will be      ////
23
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
24
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
25
//// PURPOSE.  See the GNU Lesser General Public License for more////
26
//// details. http://www.gnu.org/licenses/lgpl.html              ////
27
////                                                             ////
28
//////////////////////////////////////////////////////////////////##>
29 2 eyalhoc
 
30
##Static defines
31
SWAP MSTRS MASTER_NUM
32
SWAP SLVS EXPR(SLAVE_NUM+DVAL(DECERR_SLV))
33
 
34
LOOP MX MSTRS
35
LOOP SX SLVS
36
 
37
SWAP MSTR_BITS LOG2(MSTRS)
38
SWAP SLV_BITS  LOG2(SLVS)
39
 
40 8 eyalhoc
SWAP SERR EXPR(SLAVE_NUM-1+DVAL(DECERR_SLV))
41 2 eyalhoc
 
42
GROUP IC_AXI_A is {
43
    ID       ID_BITS                input
44
    ADDR     ADDR_BITS              input
45
    LEN      4                      input
46
    SIZE     2                      input
47
    BURST    2                      input
48
    CACHE    4                      input
49
    PROT     3                      input
50
    LOCK     2                      input
51
    USER     USER_BITS              input
52
    VALID    1                      input
53
    READY    1                      output
54
}
55
 
56
GROUP IC_AXI_W is {
57
    ID        ID_BITS                input
58
    DATA      DATA_BITS              input
59
    STRB      DATA_BITS/8            input
60
    LAST      1                      input
61
    USER      USER_BITS              input
62
    VALID     1                      input
63
    READY     1                      output
64
}
65
 
66
GROUP IC_AXI_B is {
67
    ID        ID_BITS                output
68
    RESP      2                      output
69
    USER      USER_BITS              output
70
    VALID     1                      output
71
    READY     1                      input
72
}
73
 
74
GROUP IC_AXI_R is {
75
    ID        ID_BITS                output
76
    DATA      DATA_BITS              output
77
    RESP      2                      output
78
    LAST      1                      output
79
    USER      USER_BITS              output
80
    VALID     1                      output
81
    READY     1                      input
82
}
83
 
84
GROUP IC_AXI joins {
85
    GROUP IC_AXI_A prefix_AW
86
    GROUP IC_AXI_W prefix_W
87
    GROUP IC_AXI_B prefix_B
88
    GROUP IC_AXI_A prefix_AR
89
    GROUP IC_AXI_R prefix_R
90
}
91
 
92
GROUP IC_AXI_CMD is {
93
    SLV       SLV_BITS               input
94
    ID        ID_BITS                input
95
    VALID     1                      input
96
    READY     1                      input
97
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.