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robfinch |
/* ===============================================================
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(C) 2005 Robert Finch
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All rights reserved.
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rob@birdcomputer.ca
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busTimeoutCtr.v
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Generates a timeout signal if the bus hasn't responded
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within a preset period.
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This source code is free for use and modification for
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non-commercial or evaluation purposes, provided this
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copyright statement and disclaimer remains present in
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the file.
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If you do modify the code, please state the origin and
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note that you have modified the code.
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NO WARRANTY.
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THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF
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ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
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the entire risk of using the Work.
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES
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WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR
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RELATIONSHIP WITH THE AUTHOR.
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU
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TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE
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WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED
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TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS
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OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,
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AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS
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FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED
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USE.
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The default reset state is to request the bus.
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This little circuit asserts the br line to an external
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bus when req pulses high (for a clock cycle or more) and
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removes the br signal if there is no pending req, once a
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bg has been given.
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br goes high as soon as req goes high, but then remains
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high even if req is removed.
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br goes low as soon as bg goes high UNLESS there is also
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a req present, in which case it stays high.
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br = the signal to the external bus that a request is
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present
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bg = the signal from the external bus that the bus has
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been granted
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req = signal provided by the master to indicate that it
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needs the bus. The master should monitor the bg
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signal to know when it has control of the bus.
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rdy = input indicating that the bus transaction is
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complete
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timeout = flag indicating that the request has timed out.
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Pulses high for one cycle.
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9LUTs / 8 slices
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=============================================================== */
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module busTimeoutCtr(
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input rst, // reset
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input crst, // critical reset
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input clk, // system clock
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input ce, // core clock enable
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input req, // request bus
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input rdy, // data ready input
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output timeout // timeout
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);
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parameter pTimeout = 20; // max 61
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reg [5:0] btc; // bus timeout counter
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always @(posedge clk)
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if (rst)
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btc <= 0;
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else if (ce) begin
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if (req)
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btc <= pTimeout+2;
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else if (rdy)
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btc <= 0;
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else if (btc > 0)
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btc <= btc - 1;
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end
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assign timeout = btc==6'd1;
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endmodule
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