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[/] [rtf_sprite_controller/] [trunk/] [rtl/] [verilog/] [wishbone_pkg.sv] - Blame information for rev 7

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1 7 robfinch 
// ============================================================================
2 
//        __
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//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
4 
//    \  __ /    All rights reserved.
5 
//     \/_//     robfinch@finitron.ca
6 
//       ||
7 
//
8 
// BSD 3-Clause License
9 
// Redistribution and use in source and binary forms, with or without
10 
// modification, are permitted provided that the following conditions are met:
11 
//
12 
// 1. Redistributions of source code must retain the above copyright notice, this
13 
//    list of conditions and the following disclaimer.
14 
//
15 
// 2. Redistributions in binary form must reproduce the above copyright notice,
16 
//    this list of conditions and the following disclaimer in the documentation
17 
//    and/or other materials provided with the distribution.
18 
//
19 
// 3. Neither the name of the copyright holder nor the names of its
20 
//    contributors may be used to endorse or promote products derived from
21 
//    this software without specific prior written permission.
22 
//
23 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 
//
34 
// ============================================================================
35 
//
36 
package wishbone_pkg;
37 
 
38 
typedef logic [31:0] wb_address_t;
39 
typedef logic [2:0] wb_burst_len_t;             // number of beats in a burst -1
40 
typedef logic [3:0] wb_channel_t;                       // channel for devices like system cache
41 
typedef logic [7:0] wb_tranid_t;                        // transaction id
42 
typedef logic [7:0] wb_priv_level_t;    // 0=all access,
43 
typedef logic [3:0] wb_priority_t;              // network transaction priority, higher is better
44 
 
45 
typedef enum logic [2:0] {
46 
        CLASSIC = 3'b000,
47 
        FIXED = 3'b001,                                 // constant data address
48 
        INCR = 3'b010,                                  // incrementing data address
49 
        EOB = 3'b111                                            // end of data burst
50 
} wb_cycle_type_t;
51 
 
52 
typedef enum logic [2:0] {
53 
        DATA = 3'b000,
54 
        STACK = 3'b110,
55 
        CODE = 3'b111
56 
} wb_segment_t;
57 
 
58 
typedef enum logic [2:0] {
59 
        LINEAR = 3'b000,
60 
        WRAP4 = 3'b001,
61 
        WRAP8 = 3'b010,
62 
        WRAP16 = 3'b011,
63 
        WRAP32 = 3'b100,
64 
        WRAP64 = 3'b101,
65 
        WRAP128 = 3'b110
66 
} wb_burst_type_t;
67 
 
68 
// number of byte transferred in a beat
69 
typedef enum logic [2:0] {
70 
        B8 = 3'd0,
71 
        B16 = 3'd1,
72 
        B32 = 3'd2,
73 
        B64 = 3'd3,
74 
        B128 = 3'd4
75 
} wb_size_t;
76 
 
77 
typedef enum logic [1:0] {
78 
        OKAY = 2'b00,                           // no error
79 
        DECERR = 2'd01,                 // decode error
80 
        PROTERR = 2'b10,                // security violation
81 
        ERR = 2'b11                                     // general error
82 
} wb_error_t;
83 
 
84 
typedef enum logic [3:0] {
85 
        NC_NB = 4'd0,                                                                           // Non-cacheable, non-bufferable
86 
        NON_CACHEABLE = 4'd1,
87 
        CACHEABLE_NB = 4'd2,                                            // Cacheable, non-bufferable
88 
        CACHEABLE = 4'd3,                                                               // Cacheable, bufferable
89 
        WT_NO_ALLOCATE = 4'd8,                                  // Write Through
90 
        WT_READ_ALLOCATE = 4'd9,
91 
        WT_WRITE_ALLOCATE = 4'd10,
92 
        WT_READWRITE_ALLOCATE = 4'd11,
93 
        WB_NO_ALLOCATE = 4'd12,                                 // Write Back
94 
        WB_READ_ALLOCATE = 4'd13,
95 
        WB_WRITE_ALLOCATE = 4'd14,
96 
        WB_READWRITE_ALLOCATE = 4'd15
97 
} wb_cache_t;
98 
 
99 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
100 
// Read requests
101 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
102 
 
103 
typedef struct packed {
104 
        wb_burst_type_t bte;    // burst type extension
105 
        wb_cycle_type_t cti;    // cycle type indicator
106 
        wb_burst_len_t blen;    // length of burst-1
107 
        wb_segment_t seg;                       // segment
108 
        logic cyc;                                              // valid cycle
109 
        logic stb;                                              // data strobe
110 
        wb_address_t adr;                       // address
111 
        wb_channel_t cid;                       // channel id
112 
        wb_tranid_t tid;                        // transaction id
113 
        logic sr;                                                       // set reservation
114 
        wb_priv_level_t pl;             // privilege level
115 
        wb_priority_t pri;              // transaction priority
116 
        wb_cache_t cache;                       // cache and buffer properties
117 
} wb_read_request8_t;
118 
 
119 
typedef struct packed {
120 
        wb_burst_type_t bte;    // burst type extension
121 
        wb_cycle_type_t cti;    // cycle type indicator
122 
        wb_burst_len_t blen;    // length of burst-1
123 
        wb_segment_t seg;                       // segment
124 
        logic cyc;                                              // valid cycle
125 
        logic stb;                                              // data strobe
126 
        wb_address_t adr;                       // address
127 
        logic [1:0] sel;                        // byte lane select
128 
        wb_channel_t cid;                       // channel id
129 
        wb_tranid_t tid;                        // transaction id
130 
        logic sr;                                                       // set reservation
131 
        wb_priv_level_t pl;             // privilege level
132 
        wb_priority_t pri;              // transaction priority
133 
        wb_cache_t cache;                       // cache and buffer properties
134 
} wb_read_request16_t;
135 
 
136 
typedef struct packed {
137 
        wb_burst_type_t bte;    // burst type extension
138 
        wb_cycle_type_t cti;    // cycle type indicator
139 
        wb_burst_len_t blen;    // length of burst-1
140 
        wb_segment_t seg;                       // segment
141 
        logic cyc;                                              // valid cycle
142 
        logic stb;                                              // data strobe
143 
        wb_address_t adr;                       // address
144 
        logic [3:0] sel;                        // byte lane select
145 
        wb_channel_t cid;                       // channel id
146 
        wb_tranid_t tid;                        // transaction id
147 
        logic sr;                                                       // set reservation
148 
        wb_priv_level_t pl;             // privilege level
149 
        wb_priority_t pri;              // transaction priority
150 
        wb_cache_t cache;                       // cache and buffer properties
151 
} wb_read_request32_t;
152 
 
153 
typedef struct packed {
154 
        wb_burst_type_t bte;    // burst type extension
155 
        wb_cycle_type_t cti;    // cycle type indicator
156 
        wb_burst_len_t blen;    // length of burst-1
157 
        wb_segment_t seg;                       // segment
158 
        logic cyc;                                              // valid cycle
159 
        logic stb;                                              // data strobe
160 
        wb_address_t adr;                       // address
161 
        logic [7:0] sel;                        // byte lane select
162 
        wb_channel_t cid;                       // channel id
163 
        wb_tranid_t tid;                        // transaction id
164 
        logic sr;                                                       // set reservation
165 
        wb_priv_level_t pl;             // privilege level
166 
        wb_priority_t pri;              // transaction priority
167 
        wb_cache_t cache;                       // cache and buffer properties
168 
} wb_read_request64_t;
169 
 
170 
typedef struct packed {
171 
        wb_burst_type_t bte;    // burst type extension
172 
        wb_cycle_type_t cti;    // cycle type indicator
173 
        wb_burst_len_t blen;    // length of burst-1
174 
        wb_segment_t seg;                       // segment
175 
        logic cyc;                                              // valid cycle
176 
        logic stb;                                              // data strobe
177 
        wb_address_t adr;                       // address
178 
        logic [15:0] sel;                       // byte lane select
179 
        wb_channel_t cid;                       // channel id
180 
        wb_tranid_t tid;                        // transaction id
181 
        logic sr;                                                       // set reservation
182 
        wb_priv_level_t pl;             // privilege level
183 
        wb_priority_t pri;              // transaction priority
184 
        wb_cache_t cache;                       // cache and buffer properties
185 
} wb_read_request128_t;
186 
 
187 
typedef struct packed {
188 
        wb_burst_type_t bte;    // burst type extension
189 
        wb_cycle_type_t cti;    // cycle type indicator
190 
        wb_burst_len_t blen;    // length of burst-1
191 
        wb_segment_t seg;                       // segment
192 
        logic cyc;                                              // valid cycle
193 
        logic stb;                                              // data strobe
194 
        wb_address_t adr;                       // address
195 
        logic [31:0] sel;                       // byte lane select
196 
        wb_channel_t cid;                       // channel id
197 
        wb_tranid_t tid;                        // transaction id
198 
        logic sr;                                                       // set reservation
199 
        wb_priv_level_t pl;             // privilege level
200 
        wb_priority_t pri;              // transaction priority
201 
        wb_cache_t cache;                       // cache and buffer properties
202 
} wb_read_request256_t;
203 
 
204 
typedef struct packed {
205 
        wb_burst_type_t bte;    // burst type extension
206 
        wb_cycle_type_t cti;    // cycle type indicator
207 
        wb_burst_len_t blen;    // length of burst-1
208 
        wb_segment_t seg;                       // segment
209 
        logic cyc;                                              // valid cycle
210 
        logic stb;                                              // data strobe
211 
        wb_address_t adr;                       // address
212 
        logic [63:0] sel;                       // byte lane select
213 
        wb_channel_t cid;                       // channel id
214 
        wb_tranid_t tid;                        // transaction id
215 
        logic sr;                                                       // set reservation
216 
        wb_priv_level_t pl;             // privilege level
217 
        wb_priority_t pri;              // transaction priority
218 
        wb_cache_t cache;                       // cache and buffer properties
219 
} wb_read_request512_t;
220 
 
221 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
222 
// Write requests
223 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
224 
 
225 
typedef struct packed {
226 
        wb_burst_type_t bte;    // burst type extension
227 
        wb_cycle_type_t cti;    // cycle type indicator
228 
        wb_burst_len_t blen;    // length of burst-1
229 
        wb_segment_t seg;                       // segment
230 
        logic cyc;                                              // valid cycle
231 
        logic stb;                                              // data strobe
232 
        logic we;                                                       // write enable
233 
        wb_address_t adr;                       // address
234 
        logic [7:0] dat;                        // data
235 
        wb_channel_t cid;                       // channel id
236 
        wb_tranid_t tid;                        // transaction id
237 
        logic csr;                                              // set or clear reservation we:1=clear 0=set
238 
        wb_priv_level_t pl;             // privilege level
239 
        wb_priority_t pri;              // transaction priority
240 
        wb_cache_t cache;                       // cache and buffer properties
241 
} wb_write_request8_t;
242 
 
243 
typedef struct packed {
244 
        wb_burst_type_t bte;    // burst type extension
245 
        wb_cycle_type_t cti;    // cycle type indicator
246 
        wb_burst_len_t blen;    // length of burst-1
247 
        wb_segment_t seg;                       // segment
248 
        logic cyc;                                              // valid cycle
249 
        logic stb;                                              // data strobe
250 
        logic we;                                                       // write enable
251 
        wb_address_t adr;                       // address
252 
        logic [1:0] sel;                        // byte lane selects
253 
        logic [15:0] dat;                       // data
254 
        wb_channel_t cid;                       // channel id
255 
        wb_tranid_t tid;                        // transaction id
256 
        logic csr;                                              // set or clear reservation we:1=clear 0=set
257 
        wb_priv_level_t pl;             // privilege level
258 
        wb_priority_t pri;              // transaction priority
259 
        wb_cache_t cache;                       // cache and buffer properties
260 
} wb_write_request16_t;
261 
 
262 
typedef struct packed {
263 
        wb_burst_type_t bte;    // burst type extension
264 
        wb_cycle_type_t cti;    // cycle type indicator
265 
        wb_burst_len_t blen;    // length of burst-1
266 
        wb_segment_t seg;                       // segment
267 
        logic cyc;                                              // valid cycle
268 
        logic stb;                                              // data strobe
269 
        logic we;                                                       // write enable
270 
        wb_address_t adr;                       // address
271 
        logic [3:0] sel;                        // byte lane selects
272 
        logic [31:0] dat;                       // data
273 
        wb_channel_t cid;                       // channel id
274 
        wb_tranid_t tid;                        // transaction id
275 
        logic csr;                                              // set or clear reservation we:1=clear 0=set
276 
        wb_priv_level_t pl;             // privilege level
277 
        wb_priority_t pri;              // transaction priority
278 
        wb_cache_t cache;                       // cache and buffer properties
279 
} wb_write_request32_t;
280 
 
281 
typedef struct packed {
282 
        wb_burst_type_t bte;    // burst type extension
283 
        wb_cycle_type_t cti;    // cycle type indicator
284 
        wb_burst_len_t blen;    // length of burst-1
285 
        wb_segment_t seg;                       // segment
286 
        logic cyc;                                              // valid cycle
287 
        logic stb;                                              // data strobe
288 
        logic we;                                                       // write enable
289 
        wb_address_t adr;                       // address
290 
        logic [7:0] sel;                        // byte lane selects
291 
        logic [63:0] dat;                       // data
292 
        wb_channel_t cid;                       // channel id
293 
        wb_tranid_t tid;                        // transaction id
294 
        logic csr;                                              // set or clear reservation we:1=clear 0=set
295 
        wb_priv_level_t pl;             // privilege level
296 
        wb_priority_t pri;              // transaction priority
297 
        wb_cache_t cache;                       // cache and buffer properties
298 
} wb_write_request64_t;
299 
 
300 
typedef struct packed {
301 
        wb_burst_type_t bte;    // burst type extension
302 
        wb_cycle_type_t cti;    // cycle type indicator
303 
        wb_burst_len_t blen;    // length of burst-1
304 
        wb_segment_t seg;                       // segment
305 
        logic cyc;                                              // valid cycle
306 
        logic stb;                                              // data strobe
307 
        logic we;                                                       // write enable
308 
        wb_address_t adr;                       // address
309 
        logic [15:0] sel;                       // byte lane selects
310 
        logic [127:0] dat;              // data
311 
        wb_channel_t cid;                       // channel id
312 
        wb_tranid_t tid;                        // transaction id
313 
        logic csr;                                              // set or clear reservation we:1=clear 0=set
314 
        wb_priv_level_t pl;             // privilege level
315 
        wb_priority_t pri;              // transaction priority
316 
        wb_cache_t cache;                       // cache and buffer properties
317 
} wb_write_request128_t;
318 
 
319 
typedef struct packed {
320 
        wb_burst_type_t bte;    // burst type extension
321 
        wb_cycle_type_t cti;    // cycle type indicator
322 
        wb_burst_len_t blen;    // length of burst-1
323 
        wb_segment_t seg;                       // segment
324 
        logic cyc;                                              // valid cycle
325 
        logic stb;                                              // data strobe
326 
        logic we;                                                       // write enable
327 
        wb_address_t adr;                       // address
328 
        logic [31:0] sel;                       // byte lane selects
329 
        logic [255:0] dat;              // data
330 
        wb_channel_t cid;                       // channel id
331 
        wb_tranid_t tid;                        // transaction id
332 
        logic csr;                                              // set or clear reservation we:1=clear 0=set
333 
        wb_priv_level_t pl;             // privilege level
334 
        wb_priority_t pri;              // transaction priority
335 
        wb_cache_t cache;                       // cache and buffer properties
336 
} wb_write_request256_t;
337 
 
338 
typedef struct packed {
339 
        wb_burst_type_t bte;    // burst type extension
340 
        wb_cycle_type_t cti;    // cycle type indicator
341 
        wb_burst_len_t blen;    // length of burst-1
342 
        wb_segment_t seg;                       // segment
343 
        logic cyc;                                              // valid cycle
344 
        logic stb;                                              // data strobe
345 
        logic we;                                                       // write enable
346 
        wb_address_t adr;                       // address
347 
        logic [63:0] sel;                       // byte lane selects
348 
        logic [511:0] dat;              // data
349 
        wb_channel_t cid;                       // channel id
350 
        wb_tranid_t tid;                        // transaction id
351 
        logic csr;                                              // set or clear reservation we:1=clear 0=set
352 
        wb_priv_level_t pl;             // privilege level
353 
        wb_priority_t pri;              // transaction priority
354 
        wb_cache_t cache;                       // cache and buffer properties
355 
} wb_write_request512_t;
356 
 
357 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
358 
// Read responses
359 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
360 
 
361 
typedef struct packed {
362 
        wb_channel_t cid;                       // channel id
363 
        wb_tranid_t tid;                        // transaction id
364 
        logic stall;                                    // stall pipeline
365 
        logic next;                                             // advance to next transaction
366 
        logic ack;                                              // response acknowledge
367 
        logic rty;                                              // retry
368 
        logic err;                                              // error
369 
        wb_priority_t pri;              // response priority
370 
        logic [7:0] dat;                        // data
371 
} wb_read_response8_t;
372 
 
373 
typedef struct packed {
374 
        wb_channel_t cid;                       // channel id
375 
        wb_tranid_t tid;                        // transaction id
376 
        logic stall;                                    // stall pipeline
377 
        logic next;                                             // advance to next transaction
378 
        logic ack;                                              // response acknowledge
379 
        logic rty;                                              // retry
380 
        logic err;                                              // error
381 
        wb_priority_t pri;              // response priority
382 
        logic [15:0] dat;                       // data
383 
} wb_read_response16_t;
384 
 
385 
typedef struct packed {
386 
        wb_channel_t cid;                       // channel id
387 
        wb_tranid_t tid;                        // transaction id
388 
        logic stall;                                    // stall pipeline
389 
        logic next;                                             // advance to next transaction
390 
        logic ack;                                              // response acknowledge
391 
        logic rty;                                              // retry
392 
        logic err;                                              // error
393 
        wb_priority_t pri;              // response priority
394 
        logic [31:0] dat;                       // data
395 
} wb_read_response32_t;
396 
 
397 
typedef struct packed {
398 
        wb_channel_t cid;                       // channel id
399 
        wb_tranid_t tid;                        // transaction id
400 
        logic stall;                                    // stall pipeline
401 
        logic next;                                             // advance to next transaction
402 
        logic ack;                                              // response acknowledge
403 
        logic rty;                                              // retry
404 
        logic err;                                              // error
405 
        wb_priority_t pri;              // response priority
406 
        logic [31:0] dat;                       // data
407 
} wb_response32_t;
408 
 
409 
typedef struct packed {
410 
        wb_channel_t cid;                       // channel id
411 
        wb_tranid_t tid;                        // transaction id
412 
        logic stall;                                    // stall pipeline
413 
        logic next;                                             // advance to next transaction
414 
        logic ack;                                              // response acknowledge
415 
        logic rty;                                              // retry
416 
        logic err;                                              // error
417 
        wb_priority_t pri;              // response priority
418 
        logic [63:0] dat;                       // data
419 
} wb_read_response64_t;
420 
 
421 
typedef struct packed {
422 
        wb_channel_t cid;                       // channel id
423 
        wb_tranid_t tid;                        // transaction id
424 
        logic stall;                                    // stall pipeline
425 
        logic next;                                             // advance to next transaction
426 
        logic ack;                                              // response acknowledge
427 
        logic rty;                                              // retry
428 
        logic err;                                              // error
429 
        wb_priority_t pri;              // response priority
430 
        logic [127:0] dat;              // data
431 
} wb_read_response128_t;
432 
 
433 
typedef struct packed {
434 
        wb_channel_t cid;                       // channel id
435 
        wb_tranid_t tid;                        // transaction id
436 
        logic stall;                                    // stall pipeline
437 
        logic next;                                             // advance to next transaction
438 
        logic ack;                                              // response acknowledge
439 
        logic rty;                                              // retry
440 
        logic err;                                              // error
441 
        wb_priority_t pri;              // response priority
442 
        logic [127:0] dat;              // data
443 
} wb_response128_t;
444 
 
445 
typedef struct packed {
446 
        wb_channel_t cid;                       // channel id
447 
        wb_tranid_t tid;                        // transaction id
448 
        logic stall;                                    // stall pipeline
449 
        logic next;                                             // advance to next transaction
450 
        logic ack;                                              // response acknowledge
451 
        logic rty;                                              // retry
452 
        logic err;                                              // error
453 
        wb_priority_t pri;              // response priority
454 
        logic [255:0] dat;              // data
455 
} wb_read_response256_t;
456 
 
457 
typedef struct packed {
458 
        wb_channel_t cid;                       // channel id
459 
        wb_tranid_t tid;                        // transaction id
460 
        logic stall;                                    // stall pipeline
461 
        logic next;                                             // advance to next transaction
462 
        logic ack;                                              // response acknowledge
463 
        logic rty;                                              // retry
464 
        logic err;                                              // error
465 
        wb_priority_t pri;              // response priority
466 
        logic [511:0] dat;              // data
467 
} wb_read_response512_t;
468 
 
469 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
470 
// Write responses
471 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
472 
 
473 
// Sometimes write cycles can expect data responses back too. This is typically
474 
// just a single bit. For instance, the reservation status. Write responses all
475 
// have a common structure.
476 
 
477 
typedef struct packed {
478 
        wb_channel_t cid;                       // channel id
479 
        wb_tranid_t tid;                        // transaction id
480 
        logic stall;                                    // stall pipeline
481 
        logic next;                                             // advance to next transaction
482 
        logic ack;                                              // response acknowledge
483 
        logic rty;                                              // retry
484 
        logic err;                                              // error
485 
        wb_priority_t pri;              // response priority
486 
        logic [7:0] dat;                        // data
487 
} wb_write_response_t;
488 
 
489 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
490 
// read/write requests
491 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
492 
 
493 
typedef struct packed
494 
{
495 
        wb_read_request8_t read;
496 
        wb_write_request8_t write;
497 
} wb_readwrite_request8_t;
498 
 
499 
typedef struct packed
500 
{
501 
        wb_read_request16_t read;
502 
        wb_write_request16_t write;
503 
} wb_readwrite_request16_t;
504 
 
505 
typedef struct packed
506 
{
507 
        wb_read_request32_t read;
508 
        wb_write_request32_t write;
509 
} wb_readwrite_request32_t;
510 
 
511 
typedef struct packed
512 
{
513 
        wb_read_request64_t read;
514 
        wb_write_request64_t write;
515 
} wb_readwrite_request64_t;
516 
 
517 
typedef struct packed
518 
{
519 
        wb_read_request128_t read;
520 
        wb_write_request128_t write;
521 
} wb_readwrite_request128_t;
522 
 
523 
typedef struct packed
524 
{
525 
        wb_read_request256_t read;
526 
        wb_write_request256_t write;
527 
} wb_readwrite_request256_t;
528 
 
529 
typedef struct packed
530 
{
531 
        wb_read_request512_t read;
532 
        wb_write_request512_t write;
533 
} wb_readwrite_request512_t;
534 
 
535 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
536 
// read / write responses
537 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
538 
 
539 
typedef struct packed
540 
{
541 
        wb_read_response8_t read;
542 
        wb_write_response_t write;
543 
} wb_readwrite_response8_t;
544 
 
545 
typedef struct packed
546 
{
547 
        wb_read_response16_t read;
548 
        wb_write_response_t write;
549 
} wb_readwrite_response16_t;
550 
 
551 
typedef struct packed
552 
{
553 
        wb_read_response32_t read;
554 
        wb_write_response_t write;
555 
} wb_readwrite_response32_t;
556 
 
557 
typedef struct packed
558 
{
559 
        wb_read_response64_t read;
560 
        wb_write_response_t write;
561 
} wb_readwrite_response64_t;
562 
 
563 
typedef struct packed
564 
{
565 
        wb_read_response128_t read;
566 
        wb_write_response_t write;
567 
} wb_readwrite_response128_t;
568 
 
569 
typedef struct packed
570 
{
571 
        wb_read_response256_t read;
572 
        wb_write_response_t write;
573 
} wb_readwrite_response256_t;
574 
 
575 
typedef struct packed
576 
{
577 
        wb_read_response512_t read;
578 
        wb_write_response_t write;
579 
} wb_readwrite_response512_t;
580 
 
581 
endpackage
582 
 
583 
interface wb_request_i #(int WID);
584 
        wb_burst_type_t bte;            // burst type extension
585 
        wb_cycle_type_t cti;            // cycle type indicator
586 
        wb_burst_len_t blen;            // length of burst-1
587 
        wb_segment_t seg;                               // segment
588 
        logic cyc;                                                      // valid cycle
589 
        logic stb;                                                      // data strobe
590 
        logic we;                                                               // write enable
591 
        wb_address_t adr;                               // address
592 
        logic [WID/8-1:0] sel;  // byte lane selects
593 
        logic [WID-1:0] dat;            // data
594 
        wb_channel_t cid;                               // channel id
595 
        wb_tranid_t tid;                                // transaction id
596 
        logic csr;                                                      // set or clear reservation we:1=clear 0=set
597 
        wb_priv_level_t pl;                     // privilege level
598 
        wb_priority_t pri;                      // transaction priority
599 
        wb_cache_t cache;                               // cache and buffer properties
600 
endinterface
601 
 
602 
interface wb_response_i #(int WID);
603 
        wb_channel_t cid;                               // channel id
604 
        wb_tranid_t tid;                                // transaction id
605 
        logic stall;                                            // stall pipeline
606 
        logic next;                                                     // advance to next transaction
607 
        logic ack;                                                      // response acknowledge
608 
        logic rty;                                                      // retry
609 
        logic err;                                                      // error
610 
        wb_priority_t pri;                      // response priority
611 
        logic [WID-1:0] dat;            // data
612 
endinterface

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