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// ============================================================================

//      (C) 2007,2013  Robert Finch

//  All rights reserved.

//      robfinch@<remove>finitron.ca

//

//      edge_det.v

//

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//

//    Notes:

//

//      Edge detector

//      This little core detects an edge (positive, negative, and

//      either) in the input signal.

//

//      Verilog 1995

// ============================================================================

module edge_det(rst, clk, ce, i, pe, ne, ee);

input rst;              // reset

input clk;              // clock

input ce;               // clock enable

input i;                // input signal

output pe;              // positive transition detected

output ne;              // negative transition detected

output ee;              // either edge (positive or negative) transition detected

reg ed;

always @(posedge clk)

        if (rst)

                ed <= 1'b0;

        else if (ce)

                ed <= i;

assign pe = ~ed & i;    // positive: was low and is now high

assign ne = ed & ~i;    // negative: was high and is now low

assign ee = ed ^ i;             // either: signal is now opposite to what it was

endmodule