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[/] [s6soc/] [trunk/] [rtl/] [altbusmaster.v] - Blame information for rev 13

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1 5 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    altbusmaster.v
4
//
5
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6
//
7
// Purpose:     
8
//
9
// Creator:     Dan Gisselquist, Ph.D.
10
//              Gisselquist Technology, LLC
11
//
12
////////////////////////////////////////////////////////////////////////////////
13
//
14
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
15
//
16
// This program is free software (firmware): you can redistribute it and/or
17
// modify it under the terms of  the GNU General Public License as published
18
// by the Free Software Foundation, either version 3 of the License, or (at
19
// your option) any later version.
20
//
21
// This program is distributed in the hope that it will be useful, but WITHOUT
22
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24
// for more details.
25
//
26
// You should have received a copy of the GNU General Public License along
27
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
28
// target there if the PDF file isn't present.)  If not, see
29
// <http://www.gnu.org/licenses/> for a copy.
30
//
31
// License:     GPL, v3, as defined and found on www.gnu.org,
32
//              http://www.gnu.org/licenses/gpl.html
33
//
34
//
35
////////////////////////////////////////////////////////////////////////////////
36
//
37
//
38
//
39
`include "builddate.v"
40
//
41 11 dgisselq
// `define      IMPLEMENT_ONCHIP_RAM
42 5 dgisselq
`ifndef VERILATOR
43
`define FANCY_ICAP_ACCESS
44
`endif
45
`define FLASH_ACCESS
46 8 dgisselq
`define DBG_SCOPE       // About 204 LUTs, at 2^6 addresses
47
`define INCLUDE_RTC     // About 90 LUTs
48 11 dgisselq
`define WBUBUS
49 5 dgisselq
module  altbusmaster(i_clk, i_rst,
50 8 dgisselq
                // DEPP I/O Control
51
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
52
                        i_depp_data, o_depp_data, o_depp_wait,
53
                // External UART interface
54 5 dgisselq
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
55 13 dgisselq
                        o_uart_cts,
56 5 dgisselq
                // The SPI Flash lines
57
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
58
                // The board I/O
59
                i_btn, o_led, o_pwm, o_pwm_aux,
60
                // Keypad connections
61
                i_kp_row, o_kp_col,
62
                // UART control
63
                o_uart_setup,
64
                // GPIO lines
65
                i_gpio, o_gpio);
66 8 dgisselq
        parameter       BUS_ADDRESS_WIDTH=23,
67
                        BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
68 5 dgisselq
        input                   i_clk, i_rst;
69 8 dgisselq
        // The bus commander, via an external DEPP port
70
        input                   i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
71
        input   wire    [7:0]    i_depp_data;
72
        output  wire    [7:0]    o_depp_data;
73
        output  wire            o_depp_wait;
74
        // Serial inputs
75 5 dgisselq
        input                   i_rx_stb;
76
        input           [7:0]    i_rx_data;
77 8 dgisselq
        output  reg             o_tx_stb;
78
        output  reg     [7:0]    o_tx_data;
79 5 dgisselq
        input                   i_tx_busy;
80 13 dgisselq
        output  wire            o_uart_cts;
81 5 dgisselq
        // SPI flash control
82
        output  wire            o_qspi_cs_n, o_qspi_sck;
83
        output  wire    [3:0]    o_qspi_dat;
84
        input           [3:0]    i_qspi_dat;
85
        output  wire    [1:0]    o_qspi_mod;
86
        // Board I/O
87
        input           [1:0]    i_btn;
88
        output  wire    [3:0]    o_led;
89
        output  wire            o_pwm;
90
        output  wire    [1:0]    o_pwm_aux;
91
        // Keypad
92
        input           [3:0]    i_kp_row;
93
        output  wire    [3:0]    o_kp_col;
94
        // UART control
95
        output  wire    [29:0]   o_uart_setup;
96
        // GPIO liines
97
        input           [15:0]   i_gpio;
98
        output  wire    [15:0]   o_gpio;
99
 
100
 
101
        //
102
        //
103
        // Master wishbone wires
104
        //
105
        //
106
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
107 8 dgisselq
        wire    [31:0]   wb_data, wb_idata, w_wbu_addr;
108 5 dgisselq
        wire    [(BAW-1):0]      wb_addr;
109
        wire    [5:0]            io_addr;
110
        assign  io_addr = {
111
                        wb_addr[22],    // Flash
112
                        wb_addr[13],    // RAM
113
                        wb_addr[11],    // RTC
114
                        wb_addr[10],    // CFG
115
                        wb_addr[ 9],    // SCOPE
116
                        wb_addr[ 8] };  // I/O
117
 
118
        // Wires going to devices
119
        // And then headed back home
120
        wire    w_interrupt;
121 8 dgisselq
`ifdef  WBUBUS
122 5 dgisselq
        //
123
        //
124
        // The BUS master (source): The WB to UART conversion bus
125
        //
126
        //
127 11 dgisselq
        wire            dep_rx_stb, dep_tx_stb, dep_tx_busy;
128
        wire    [7:0]    dep_rx_data, dep_tx_data;
129
        deppbyte        deppdrive(i_clk,
130
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
131
                        i_depp_data, o_depp_data, o_depp_wait,
132
                dep_rx_stb, dep_rx_data,
133
                dep_tx_stb, dep_tx_data, dep_tx_busy);
134
 
135
        wbubus busbdriver(i_clk,
136
                        // i_rx_stb, i_rx_data,         // UART control
137
                        dep_rx_stb, dep_rx_data,        // DEPP control
138 5 dgisselq
                        // The wishbone interface
139
                        wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
140
                                wb_ack, wb_stall, wb_err, wb_idata,
141
                        w_interrupt,
142 11 dgisselq
                        // Provide feedback to the DEPP interface
143
                        dep_tx_stb, dep_tx_data, dep_tx_busy);
144
//                      // Provide feedback to the UART
145
//                      o_tx_stb, o_tx_data, i_tx_busy
146
        // assign       o_uart_rts = (~rx_rdy);
147 8 dgisselq
`else
148
        //
149
        //
150
        // Another BUS master (source): A conversion from DEPP to busmaster
151
        //
152
        //
153
        wbdeppsimple    deppdrive(i_clk,
154
                i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
155
                        i_depp_data, o_depp_data, o_depp_wait,
156
                wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
157
                        wb_ack, wb_stall, wb_err, wb_idata,
158
                        w_interrupt);
159
`endif
160 5 dgisselq
 
161
        generate
162 8 dgisselq
        if (BAW < 32)
163
                assign  wb_addr = w_wbu_addr[(BAW-1):0];
164 5 dgisselq
        else
165 8 dgisselq
                assign  wb_addr = w_wbu_addr;
166 5 dgisselq
        endgenerate
167
 
168
        wire    io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
169
                        rtc_sel, none_sel, many_sel;
170
        wire    flash_ack, scop_ack, cfg_ack, mem_ack;
171
        wire    rtc_ack, rtc_stall;
172
`ifdef  INCLUDE_RTC
173
        assign  rtc_stall = 1'b0;
174
`endif
175
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
176 8 dgisselq
        reg     io_ack;
177 5 dgisselq
 
178
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
179
                        spio_data, gpio_data, uart_data;
180
        reg     [31:0]   io_data;
181
        reg     [(BAW-1):0]      bus_err_addr;
182
 
183
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
184
`ifdef  INCLUDE_RTC
185
                                ||(rtc_ack)
186
`endif
187
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
188
        assign  wb_stall = ((io_sel)&&(io_stall))
189
                        ||((scop_sel)&&(scop_stall))
190
                        ||((cfg_sel)&&(cfg_stall))
191
                        ||((mem_sel)&&(mem_stall))
192
`ifdef  INCLUDE_RTC
193
                        ||((rtc_sel)&&(rtc_stall))
194
`endif
195
                        ||((flash_sel||flctl_sel)&&(flash_stall));
196
                        // (none_sel)&&(1'b0)
197
 
198
        /*
199
        assign  wb_idata = (io_ack)?io_data
200
                        : ((scop_ack)?scop_data
201
                        : ((cfg_ack)?cfg_data
202
                        : ((mem_ack)?mem_data
203
                        : ((flash_ack)?flash_data
204
                        : 32'h00))));
205
        */
206
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
207
                        : ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
208 8 dgisselq
                        : ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
209 5 dgisselq
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
210
 
211
        // Addresses ...
212
        //      0000 xxxx       configuration/control registers
213
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
214
        assign  io_sel   =((wb_cyc)&&(io_addr[5:0]==6'h1));
215 8 dgisselq
        assign  scop_sel =((wb_cyc)&&(io_addr[5:0]==6'h2));
216
        assign  flctl_sel=((wb_cyc)&&(io_addr[5:0]==6'h3));
217
        assign  cfg_sel  =((wb_cyc)&&(io_addr[5:1]==5'h2));
218 5 dgisselq
        // zip_sel is not on the bus at this point
219
`ifdef  INCLUDE_RTC
220
        assign  rtc_sel  =((wb_cyc)&&(io_addr[5:3]==3'h1));
221
`endif
222
        assign  mem_sel  =((wb_cyc)&&(io_addr[5:4]==2'h1));
223
        assign  flash_sel=((wb_cyc)&&(io_addr[5]));
224
 
225
        assign  none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
226
        assign  many_sel =((wb_cyc)&&(wb_stb)&&(
227
                         {3'h0, io_sel}
228
                        +{3'h0, flctl_sel}
229 8 dgisselq
                        +{3'h0, scop_sel}
230 5 dgisselq
                        +{3'h0, cfg_sel}
231 8 dgisselq
                        +{3'h0, rtc_sel}
232 5 dgisselq
                        +{3'h0, mem_sel}
233
                        +{3'h0, flash_sel} > 1));
234 8 dgisselq
        // assign       many_sel = 1'b0;
235 5 dgisselq
 
236
        wire    many_ack;
237
        assign  many_ack =((wb_cyc)&&(
238
                         {3'h0, io_ack}
239
                        +{3'h0, scop_ack}
240
                        +{3'h0, cfg_ack}
241
`ifdef  INCLUDE_RTC
242
                        +{3'h0, rtc_ack}
243
`endif
244
                        +{3'h0, mem_ack}
245
                        +{3'h0, flash_ack} > 1));
246
 
247
        wire            flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
248
                        rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
249
 
250
 
251
        //
252
        //
253
        //
254
        reg             rx_rdy;
255 11 dgisselq
        wire    [11:0]   int_vector;
256
        assign  int_vector = { flash_interrupt, gpio_int, pwm_int, keypad_int,
257 13 dgisselq
                                (~o_tx_stb), rx_rdy,
258
                                tmrb_int, tmra_int,
259 5 dgisselq
                                rtc_interrupt, scop_interrupt,
260
                                wb_err, button_int };
261
 
262
        wire    [31:0]   pic_data;
263 11 dgisselq
        icontrol #(12)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
264 5 dgisselq
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
265
                        wb_data, pic_data, int_vector, w_interrupt);
266
 
267 8 dgisselq
        initial bus_err_addr = 0; // `DATESTAMP;
268 5 dgisselq
        always @(posedge i_clk)
269
                if (wb_err)
270
                        bus_err_addr <= wb_addr;
271
 
272 11 dgisselq
        wire    [31:0]   timer_a, timer_b;
273 5 dgisselq
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
274 13 dgisselq
        ziptimer        #(32,31)
275 8 dgisselq
                zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
276 5 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
277
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
278
                                tmra_int);
279 13 dgisselq
        ziptimer        #(32,31)
280 8 dgisselq
                zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
281 5 dgisselq
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
282
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
283
                                tmrb_int);
284
 
285
        wire    [31:0]   rtc_data;
286
`ifdef  INCLUDE_RTC
287
        wire    rtcd_ack, rtcd_stall, ppd;
288
        // rtcdate      thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
289
                        // wb_data, rtcd_ack, rtcd_stall, date_data);
290
        reg     r_rtc_ack;
291
        initial r_rtc_ack = 1'b0;
292
        always @(posedge i_clk)
293
                r_rtc_ack <= ((wb_stb)&&(rtc_sel));
294
        assign  rtc_ack = r_rtc_ack;
295
 
296
        rtclight
297 8 dgisselq
                #(23'h35afe5,23,0,0)      // 80 MHz clock
298 5 dgisselq
                thetime(i_clk, wb_cyc,
299
                        ((wb_stb)&&(rtc_sel)), wb_we,
300
                        { 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
301
                        rtc_interrupt, ppd);
302
`else
303
        assign  rtc_interrupt = 1'b0;
304
        assign  rtc_data = 32'h00;
305
        assign  rtc_ack  = 1'b0;
306
`endif
307
 
308
        always @(posedge i_clk)
309
                case(wb_addr[3:0])
310
                        4'h0: io_data <= pic_data;
311
                        4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
312
                        4'h2: io_data <= timer_a;
313
                        4'h3: io_data <= timer_b;
314
                        4'h4: io_data <= pwm_data;
315
                        4'h5: io_data <= spio_data;
316
                        4'h6: io_data <= gpio_data;
317
                        4'h7: io_data <= uart_data;
318
                        default: io_data <= `DATESTAMP;
319
                        // 4'h8: io_data <= `DATESTAMP;
320
                endcase
321
        always @(posedge i_clk)
322
                io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
323
        assign  io_stall = 1'b0;
324
 
325
        wire    pwm_ack, pwm_stall;
326 13 dgisselq
        wbpwmaudio      #(14'd10000,2,0,14)
327
                theaudio(i_clk, wb_cyc,
328
                                ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
329
                                        wb_we, 1'b0, wb_data,
330
                                pwm_ack, pwm_stall, pwm_data, o_pwm,
331
                                        o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
332
                                        pwm_int);
333 5 dgisselq
 
334
        //
335
        // Special Purpose I/O: Keypad, button, LED status and control
336
        //
337
        spio    thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
338
                        wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
339
                        keypad_int, button_int);
340
 
341
        //
342
        // General purpose (sort of) I/O:  (Bottom two bits robbed in each
343
        // direction for an I2C link at the toplevel.v design)
344
        //
345
        wbgpio  #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
346
                        (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
347
                        wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
348
 
349
        //
350
        //
351
        //      Rudimentary serial port control
352
        //
353
        reg     [7:0]    r_rx_data;
354
        // Baud rate is set by clock rate / baud rate.
355
        // Thus, 80MHz / 115200MBau
356
        //      = 694.4, or about 0x2b6. 
357
        // although the CPU might struggle to keep up at this speed without a
358
        // hardware buffer.
359
        //
360
        // We'll add the flag for two stop bits.
361 8 dgisselq
        // assign       o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
362
        assign  o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
363 5 dgisselq
 
364 8 dgisselq
        initial o_tx_stb = 1'b0;
365
        initial o_tx_data = 8'h00;
366
        always @(posedge i_clk)
367
                if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
368
                begin
369
                        o_tx_data <= wb_data[7:0];
370
                        o_tx_stb <= 1'b1;
371
                end
372
                else if ((o_tx_stb)&&(~i_tx_busy))
373
                        o_tx_stb <= 1'b0;
374
        initial rx_rdy = 1'b0;
375
        always @(posedge i_clk)
376
                if (i_rx_stb)
377
                        r_rx_data <= i_rx_data;
378
        always @(posedge i_clk)
379
        begin
380
                if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
381
                        rx_rdy <= i_rx_stb;
382
                else if (i_rx_stb)
383
                        rx_rdy <= (rx_rdy | i_rx_stb);
384
        end
385 13 dgisselq
        assign  o_uart_cts = (~rx_rdy);
386 8 dgisselq
        assign  uart_data = { 23'h0, ~rx_rdy, r_rx_data };
387
        //
388
        // uart_ack gets returned as part of io_ack, since that happens when
389
        // io_sel and wb_stb are defined
390
        //
391
        // always @(posedge i_clk)
392
                // uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
393 5 dgisselq
 
394
 
395
 
396
        //
397
        //      FLASH MEMORY CONFIGURATION ACCESS
398
        //
399
        wbqspiflashp #(24)      flashmem(i_clk,
400 11 dgisselq
                wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
401 8 dgisselq
                        wb_addr[(24-3):0], wb_data,
402 5 dgisselq
                flash_ack, flash_stall, flash_data,
403
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
404
                flash_interrupt);
405
 
406
        //
407
        //      MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
408
        //
409
        wire    [31:0]   cfg_scope;
410
`ifdef  FANCY_ICAP_ACCESS
411
        wbicape6        fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
412
                                wb_addr[5:0], wb_data,
413
                                cfg_ack, cfg_stall, cfg_data,
414
                                cfg_scope);
415
`else
416
        reg     r_cfg_ack;
417
        always @(posedge i_clk)
418
                r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
419
        assign  cfg_ack   = r_cfg_ack;
420
        assign  cfg_stall = 1'b0;
421
        assign  cfg_data  = 32'h00;
422
        assign  cfg_scope = 32'h00;
423
`endif
424
 
425
 
426
        //
427
        //      ON-CHIP RAM MEMORY ACCESS
428
        //
429 8 dgisselq
`ifdef  IMPLEMENT_ONCHIP_RAM
430 5 dgisselq
        memdev  #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
431
                        wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
432 8 dgisselq
`else
433
        assign  mem_data = 32'h00;
434
        assign  mem_stall = 1'b0;
435
        reg     r_mem_ack;
436
        always @(posedge i_clk)
437
                r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
438
        assign  mem_ack = r_mem_ack;
439
`endif
440 5 dgisselq
 
441
        //
442
        //
443
        //      WISHBONE SCOPE
444
        //
445
        //
446
        //
447
        //
448
        wire    [31:0]   scop_cfg_data;
449
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
450 8 dgisselq
`ifdef  DBG_SCOPE
451 5 dgisselq
        wire            scop_cfg_trigger;
452
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
453
        wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
454
                // Wishbone interface
455 8 dgisselq
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
456 5 dgisselq
                                wb_we, wb_addr[0], wb_data,
457
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
458
                scop_cfg_interrupt);
459 8 dgisselq
`else
460
        reg     r_scop_cfg_ack;
461
        always @(posedge i_clk)
462
                r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
463
        assign  scop_cfg_ack = r_scop_cfg_ack;
464
        assign  scop_cfg_data = 32'h000;
465
        assign  scop_cfg_stall= 1'b0;
466 5 dgisselq
`endif
467
 
468
        assign  scop_interrupt = scop_cfg_interrupt;
469
        assign  scop_ack   = scop_cfg_ack;
470
        assign  scop_stall = scop_cfg_stall;
471
        assign  scop_data  = scop_cfg_data;
472
 
473
endmodule
474
 

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