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[/] [s6soc/] [trunk/] [rtl/] [busmaster.v] - Blame information for rev 2

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1 2 dgisselq
//
2
//
3
// Filename:    busmaster.v
4
//
5
// Project:     FPGA library development (S6 development board)
6
//
7
// Purpose:
8
//
9
// Creator:     Dan Gisselquist
10
//              Gisselquist Technology, LLC
11
//
12
// Copyright:   2015
13
//
14
//
15
`include "builddate.v"
16
//
17
`define NO_ZIP_WBU_DELAY
18
`define INCLUDE_ZIPPY
19
`define IMPLEMENT_ONCHIP_RAM
20
`ifndef VERILATOR
21
`define FANCY_ICAP_ACCESS
22
`endif
23
`define FLASH_ACCESS
24
`define CFG_SCOPE
25
`define INCLUDE_RTC     // 2017 slice LUTs w/o, 2108 with (!!!)
26
module  busmaster(i_clk, i_rst,
27
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
28
                // The SPI Flash lines
29
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
30
                // The board I/O
31
                i_btn, o_led, o_pwm, o_pwm_aux,
32
                // Keypad connections
33
                i_kp_row, o_kp_col,
34
                // UART control
35
                o_uart_setup,
36
                // GPIO lines
37
                i_gpio, o_gpio);
38
        parameter       ZIP_ADDRESS_WIDTH=23, ZA=ZIP_ADDRESS_WIDTH,
39
                        CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
40
                        BUS_ADDRESS_WIDTH=23, BAW=23; // 24bits->2,258,23b->2181
41
        input                   i_clk, i_rst;
42
        // The bus commander, via an external JTAG port
43
        input                   i_rx_stb;
44
        input           [7:0]    i_rx_data;
45
        output  reg             o_tx_stb;
46
        output  reg     [7:0]    o_tx_data;
47
        input                   i_tx_busy;
48
        // SPI flash control
49
        output  wire            o_qspi_cs_n, o_qspi_sck;
50
        output  wire    [3:0]    o_qspi_dat;
51
        input           [3:0]    i_qspi_dat;
52
        output  wire    [1:0]    o_qspi_mod;
53
        // Board I/O
54
        input           [1:0]    i_btn;
55
        output  wire    [3:0]    o_led;
56
        output  wire            o_pwm;
57
        output  wire    [1:0]    o_pwm_aux;
58
        // Keypad
59
        input           [3:0]    i_kp_row;
60
        output  wire    [3:0]    o_kp_col;
61
        // UART control
62
        output  wire    [29:0]   o_uart_setup;
63
        // GPIO liines
64
        input           [15:0]   i_gpio;
65
        output  wire    [15:0]   o_gpio;
66
 
67
 
68
        //
69
        //
70
        // Master wishbone wires
71
        //
72
        //
73
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
74
        wire    [31:0]   wb_data, wb_idata;
75
        wire    [(BAW-1):0]      wb_addr;
76
        wire    [5:0]            io_addr;
77
        assign  io_addr = {
78
                        wb_addr[22],    // Flash
79
                        wb_addr[13],    // RAM
80
                        wb_addr[11],    // RTC
81
                        wb_addr[10],    // CFG
82
                        wb_addr[ 9],    // SCOPE
83
                        wb_addr[ 8] };  // I/O
84
 
85
        // Wires going to devices
86
        // And then headed back home
87
        wire    w_interrupt;
88
        // Oh, and the debug control for the ZIP CPU
89
        wire            zip_dbg_ack, zip_dbg_stall;
90
        wire    [31:0]   zip_dbg_data;
91
 
92
 
93
        //
94
        //
95
        // The BUS master (source): The ZipCPU
96
        //
97
        //
98
        wire            zip_cyc, zip_stb, zip_we, zip_cpu_int;
99
        wire    [(ZA-1):0]       w_zip_addr;
100
        wire    [(BAW-1):0]      zip_addr;
101
        wire    [31:0]           zip_data;
102
        // and then coming from devices
103
        wire            zip_ack, zip_stall, zip_err;
104
        wire    dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
105
        wire    [(BAW-1):0]      dwb_addr;
106
        wire    [31:0]           dwb_odata;
107
 
108
        // wire [31:0]  zip_debug;
109
//
110
// We'll define our RESET_ADDRESS to be halfway through our flash memory.
111
//      `define CMOD_ZIPCPU_RESET_ADDRESS       23'h600000
112
//
113
// Ahm, No.  We can actually do much better than that.  Our toplevel *.bit file
114
// only takes up only 335kB.  Let's give it some room to grow to 1024 kB.  Then
115
// 23 can start our ROM at 23'h400100
116
//
117
// Not so fast.  In hindsight, we really want to be  able to adjust the load and
118
// the program separately.  So, instead, let's place our RESET address at the
119
// second flash erase block.  That way, we can change our program code found
120
// in the flash without needing to change our FPGA load and vice versa.
121
//
122
// 23'h404000
123
        zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
124
                thecpu(i_clk, 1'b0,
125
                        // Zippys wishbone interface
126
                        wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data,
127
                                wb_ack, wb_stall, wb_idata, wb_err,
128
                        w_interrupt, zip_cpu_int,
129
                        // Debug wishbone interface
130
                        1'b0, 1'b0,1'b0, 1'b0, 32'h00,
131
                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data);
132
        generate
133
        if (ZA < BAW)
134
                assign  wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
135
        else
136
                assign  wb_addr = w_zip_addr;
137
        endgenerate
138
 
139
        wire    io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
140
                        rtc_sel, none_sel, many_sel;
141
        wire    flash_ack, scop_ack, cfg_ack, mem_ack;
142
        wire    rtc_ack, rtc_stall;
143
`ifdef  INCLUDE_RTC
144
        assign  rtc_stall = 1'b0;
145
`endif
146
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
147
        reg     io_ack, uart_ack;
148
 
149
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
150
                        spio_data, gpio_data, uart_data;
151
        reg     [31:0]   io_data;
152
        reg     [(BAW-1):0]      bus_err_addr;
153
 
154
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
155
                                ||(uart_ack)
156
`ifdef  INCLUDE_RTC
157
                                ||(rtc_ack)
158
`endif
159
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
160
        assign  wb_stall = ((io_sel)&&(io_stall))
161
                        ||((scop_sel)&&(scop_stall))
162
                        ||((cfg_sel)&&(cfg_stall))
163
                        ||((mem_sel)&&(mem_stall))
164
`ifdef  INCLUDE_RTC
165
                        ||((rtc_sel)&&(rtc_stall))
166
`endif
167
                        ||((flash_sel||flctl_sel)&&(flash_stall));
168
                        // (none_sel)&&(1'b0)
169
 
170
        /*
171
        assign  wb_idata = (io_ack)?io_data
172
                        : ((scop_ack)?scop_data
173
                        : ((cfg_ack)?cfg_data
174
                        : ((mem_ack)?mem_data
175
                        : ((flash_ack)?flash_data
176
                        : 32'h00))));
177
        */
178
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
179
                        : ((cfg_ack|uart_ack) ? ((cfg_ack)?cfg_data: uart_data)
180
                        : ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
181
                        : flash_data)); // if (flash_ack)
182
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
183
 
184
        // Addresses ...
185
        //      0000 xxxx       configuration/control registers
186
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
187
        assign  io_sel   =((wb_cyc)&&(io_addr[5:0]==6'h1));
188
        assign  flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
189
        assign  scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
190
        assign  cfg_sel  =((wb_cyc)&&(io_addr[5:2]==4'h1));
191
        // zip_sel is not on the bus at this point
192
`ifdef  INCLUDE_RTC
193
        assign  rtc_sel  =((wb_cyc)&&(io_addr[5:3]==3'h1));
194
`endif
195
        assign  mem_sel  =((wb_cyc)&&(io_addr[5:4]==2'h1));
196
        assign  flash_sel=((wb_cyc)&&(io_addr[5]));
197
 
198
        assign  none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
199
        /*
200
        assign  many_sel =((wb_cyc)&&(wb_stb)&&(
201
                         {3'h0, io_sel}
202
                        +{3'h0, flctl_sel}
203
                        // +{3'h0, scop_sel}
204
                        +{3'h0, cfg_sel}
205
                        +{3'h0, mem_sel}
206
                        +{3'h0, flash_sel} > 1));
207
        */
208
        assign  many_sel = 1'b0;
209
 
210
        wire    many_ack;
211
        assign  many_ack =((wb_cyc)&&(
212
                         {3'h0, io_ack}
213
                        +{3'h0, scop_ack}
214
                        +{3'h0, cfg_ack}
215
`ifdef  INCLUDE_RTC
216
                        +{3'h0, rtc_ack}
217
`endif
218
                        +{3'h0, mem_ack}
219
                        +{3'h0, flash_ack} > 1));
220
 
221
        wire            flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
222
                        rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
223
 
224
 
225
        //
226
        //
227
        //
228
        reg             rx_rdy;
229
        wire    [10:0]   int_vector;
230
        assign  int_vector = { gpio_int, pwm_int, keypad_int,
231
                                ~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
232
                                rtc_interrupt, scop_interrupt,
233
                                wb_err, button_int };
234
 
235
        wire    [31:0]   pic_data;
236
        icontrol #(11)  pic(i_clk, 1'b0,
237
                                (wb_cyc)&&(wb_stb)&&(io_sel)
238
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
239
                        wb_data, pic_data, int_vector, w_interrupt);
240
 
241
        initial bus_err_addr = `DATESTAMP;
242
        always @(posedge i_clk)
243
                if (wb_err)
244
                        bus_err_addr <= wb_addr;
245
 
246
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
247
        wire    [31:0]   timer_a, timer_b;
248
        ziptimer        zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
249
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
250
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
251
                                tmra_int);
252
        ziptimer        zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
253
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
254
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
255
                                tmrb_int);
256
 
257
        wire    [31:0]   rtc_data;
258
`ifdef  INCLUDE_RTC
259
        wire    rtcd_ack, rtcd_stall, ppd;
260
        // rtcdate      thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
261
                        // wb_data, rtcd_ack, rtcd_stall, date_data);
262
        reg     r_rtc_ack;
263
        initial r_rtc_ack = 1'b0;
264
        always @(posedge i_clk)
265
                r_rtc_ack <= ((wb_stb)&&(rtc_sel));
266
        assign  rtc_ack = r_rtc_ack;
267
 
268
        rtclight
269
                #(32'h35afe5)           // 80 MHz clock
270
                thetime(i_clk, wb_cyc,
271
                        ((wb_stb)&&(rtc_sel)), wb_we,
272
                        { 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
273
                        rtc_interrupt, ppd);
274
`else
275
        assign  rtc_interrupt = 1'b0;
276
        assign  rtc_data = 32'h00;
277
        assign  rtc_ack  = 1'b0;
278
`endif
279
 
280
        always @(posedge i_clk)
281
                case(wb_addr[3:0])
282
                        4'h0: io_data <= pic_data;
283
                        4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
284
                        4'h2: io_data <= timer_a;
285
                        4'h3: io_data <= timer_b;
286
                        4'h4: io_data <= pwm_data;
287
                        4'h5: io_data <= spio_data;
288
                        4'h6: io_data <= gpio_data;
289
                        4'h7: io_data <= uart_data;
290
                        default: io_data <= `DATESTAMP;
291
                        // 4'h8: io_data <= `DATESTAMP;
292
                endcase
293
        always @(posedge i_clk)
294
                io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
295
        assign  io_stall = 1'b0;
296
 
297
        wire    pwm_ack, pwm_stall;
298
        wbpwmaudio      theaudio(i_clk, wb_cyc,
299
                                ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)), wb_we,
300
                                1'b0, wb_data,
301
                                pwm_ack, pwm_stall, pwm_data, o_pwm, o_pwm_aux,
302
                                pwm_int);
303
 
304
        //
305
        // Special Purpose I/O: Keypad, button, LED status and control
306
        //
307
        spio    thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
308
                        wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
309
                        keypad_int, button_int);
310
 
311
        //
312
        // General purpose (sort of) I/O:  (Bottom two bits robbed in each
313
        // direction for an I2C link at the toplevel.v design)
314
        //
315
        wbgpio  #(16,16,16'hffff) thegpio(i_clk, wb_cyc,
316
                        (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
317
                        wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
318
 
319
        //
320
        //
321
        //      Rudimentary serial port control
322
        //
323
        reg     [7:0]    r_rx_data;
324
        // Baud rate is set by clock rate / baud rate.
325
        // Thus, 80MHz / 115200MBau
326
        //      = 694.4, or about 0x2b6. 
327
        // although the CPU might struggle to keep up at this speed without a
328
        // hardware buffer.
329
        //
330
        // We'll add the flag for two stop bits.
331
        assign  o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
332
 
333
        initial o_tx_stb = 1'b0;
334
        initial o_tx_data = 8'h00;
335
        always @(posedge i_clk)
336
                if ((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
337
                begin
338
                        o_tx_data <= wb_data[7:0];
339
                        o_tx_stb <= 1'b1;
340
                end
341
                else if ((o_tx_stb)&&(~i_tx_busy))
342
                        o_tx_stb <= 1'b0;
343
        initial rx_rdy = 1'b0;
344
        always @(posedge i_clk)
345
                if (i_rx_stb)
346
                        r_rx_data <= i_rx_data;
347
        always @(posedge i_clk)
348
        begin
349
                if((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
350
                        rx_rdy <= i_rx_stb;
351
                else if (i_rx_stb)
352
                        rx_rdy <= (rx_rdy | i_rx_stb);
353
        end
354
        assign  uart_data = { 23'h0, ~rx_rdy, r_rx_data };
355
        always @(posedge i_clk)
356
                uart_ack<= ((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
357
 
358
 
359
 
360
        //
361
        //      FLASH MEMORY CONFIGURATION ACCESS
362
        //
363
        wire    flash_cs_n, flash_sck, flash_mosi;
364
        wbqspiflash #(24)       flashmem(i_clk,
365
                wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
366
                        wb_addr[21:0], wb_data,
367
                flash_ack, flash_stall, flash_data,
368
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
369
                flash_interrupt);
370
 
371
        //
372
        //      MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
373
        //
374
        wire    [31:0]   cfg_scope;
375
`ifdef  FANCY_ICAP_ACCESS
376
        wbicape6        fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
377
                                wb_addr[5:0], wb_data,
378
                                cfg_ack, cfg_stall, cfg_data,
379
                                cfg_scope);
380
`else
381
        reg     r_cfg_ack;
382
        always @(posedge i_clk)
383
                r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
384
        assign  cfg_ack   = r_cfg_ack;
385
        assign  cfg_stall = 1'b0;
386
        assign  cfg_data  = 32'h00;
387
        assign  cfg_scope = 32'h00;
388
`endif
389
 
390
 
391
        //
392
        //      ON-CHIP RAM MEMORY ACCESS
393
        //
394
        memdev  #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
395
                        wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
396
 
397
        //
398
        //
399
        //      WISHBONE SCOPE
400
        //
401
        //
402
        //
403
        //
404
        wire    [31:0]   scop_cfg_data;
405
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
406
`ifdef  CFG_SCOPE
407
        wire            scop_cfg_trigger;
408
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
409
        wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
410
                // Wishbone interface
411
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
412
                                wb_we, wb_addr[0], wb_data,
413
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
414
                scop_cfg_interrupt);
415
`endif
416
 
417
        assign  scop_interrupt = scop_cfg_interrupt;
418
        assign  scop_ack   = scop_cfg_ack;
419
        assign  scop_stall = scop_cfg_stall;
420
        assign  scop_data  = scop_cfg_data;
421
 
422
endmodule
423
 
424
// 0x8684 interrupts ...???

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