OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [deppbyte.v] - Blame information for rev 46

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    deppbyte.v
4
//
5
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6
//
7
// Purpose:     This is a very simple DEPP to synchronous byte transfer.  It
8
//              is used in place of a serial port.
9
//
10
//      This approach uses address zero *only*.
11
//
12
// Creator:     Dan Gisselquist, Ph.D.
13
//              Gisselquist Technology, LLC
14
//
15
////////////////////////////////////////////////////////////////////////////////
16
//
17 46 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
18 11 dgisselq
//
19
// This program is free software (firmware): you can redistribute it and/or
20
// modify it under the terms of  the GNU General Public License as published
21
// by the Free Software Foundation, either version 3 of the License, or (at
22
// your option) any later version.
23
//
24
// This program is distributed in the hope that it will be useful, but WITHOUT
25
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
26
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
27
// for more details.
28
//
29
// You should have received a copy of the GNU General Public License along
30 46 dgisselq
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
31 11 dgisselq
// target there if the PDF file isn't present.)  If not, see
32
// <http://www.gnu.org/licenses/> for a copy.
33
//
34
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38
////////////////////////////////////////////////////////////////////////////////
39
//
40
//
41
module deppbyte(i_clk,
42
        i_astb_n, i_dstb_n, i_write_n,i_depp, o_depp, o_wait,
43
        o_rx_stb, o_rx_data,
44
        i_tx_stb, i_tx_data, o_tx_busy);
45
        input   i_clk;
46
        // DEPP interface
47
        input                   i_astb_n, i_dstb_n, i_write_n;
48
        input           [7:0]    i_depp;
49
        output  reg     [7:0]    o_depp;
50
        output  wire            o_wait;
51
        // Byte-wise interface to the rest of the world
52
        output  reg             o_rx_stb;
53
        output  reg     [7:0]    o_rx_data;
54
        input                   i_tx_stb;
55
        input           [7:0]    i_tx_data;
56
        output  reg             o_tx_busy;
57
 
58
        // Synchronize the incoming signals
59
        reg     x_dstb_n, x_astb_n, x_write_n,
60
                r_dstb_n, r_astb_n, r_write_n,
61
                l_dstb_n, l_astb_n, l_write_n;
62
        reg     [7:0]    x_depp, r_depp;
63
        initial x_dstb_n = 1'b1;
64
        initial r_dstb_n = 1'b1;
65
        initial l_dstb_n = 1'b1;
66
        initial x_astb_n = 1'b1;
67
        initial r_astb_n = 1'b1;
68
        initial l_astb_n = 1'b1;
69
        always @(posedge i_clk)
70
        begin
71
                { x_dstb_n, x_astb_n, x_write_n, x_depp }
72
                        <= { i_dstb_n, i_astb_n, i_write_n, i_depp };
73
                { r_dstb_n, r_astb_n, r_write_n, r_depp }
74
                        <= { x_dstb_n, x_astb_n, x_write_n, x_depp };
75
                { l_dstb_n, l_astb_n, l_write_n } <= { r_dstb_n, r_astb_n, r_write_n };
76
        end
77
 
78
        reg     [7:0]    addr;
79
        wire    astb, dstb, w_write;
80 46 dgisselq
        assign  astb = (!r_astb_n)&&(l_astb_n);
81
        assign  dstb = (!r_dstb_n)&&(l_dstb_n);
82
        assign  w_write= (!r_write_n);
83 11 dgisselq
 
84
 
85
        initial addr = 8'h00;
86
        initial o_rx_stb = 1'b0;
87
        always @(posedge i_clk)
88
        begin
89
                if ((w_write)&&(astb))
90
                        addr <= r_depp;
91
 
92
                if ((w_write)&&(dstb)&&(addr==0))
93
                begin
94
                        o_rx_stb  <= 1'b1;
95
                        o_rx_data <= r_depp;
96
                end else
97
                        o_rx_stb <= 1'b0;
98
        end
99
 
100
        // Much as I hate to use signals that have not been synchronized with a 
101
        // two clock transfer, this line needs to be brought low within 10ms
102
        // (less than one clock) of when the strobe lines are brought low, and
103
        // raised high again within 10 ms of when the strobe lines are raised
104
        // again.
105 46 dgisselq
        assign  o_wait = ((!i_dstb_n)||(!i_astb_n));
106 11 dgisselq
 
107
        // For one clock, following any read from address zero, we allow the
108
        // port to write one new byte into our interface.  This works because
109
        // the interface will guarantee that the strobe signals are inactive
110
        // (high) for at least 40ns before attempting a new transaction.
111
        //
112
        // Just about nothing else works.  'cause we can't allow changes
113
        // in the middle of a transaction, and we won't know if the clock
114
        // involved is in the middle of a transaction until after the time
115
        // has passed.  Therefore, we're going to be busy most of the time
116
        // and just allow a byte to pass through on the one (and only) clock
117
        // following a transaction.
118
        always @(posedge i_clk)
119
                o_tx_busy <= ((~l_dstb_n)&&(r_dstb_n)&&(l_write_n)&&(addr == 0))
120
                                ? 1'b0 : 1'b1;
121
 
122
        // If we don't have a byte to write, stuff it with all ones.  The high
123
        // bit will then indicate that there's nothing available to the 
124
        // interface when it next reads.
125
        //
126
        // Okay, new philosophy.  Stuff the high bit with ones, allow the other
127
        // bits to contain status level information --- should any one wish to
128
        // send such.
129
        initial o_depp = 8'hff;
130
        always @(posedge i_clk)
131
                if (~o_tx_busy)
132
                        o_depp <= {((i_tx_stb)? i_tx_data[7] : 1'b1),
133
                                        i_tx_data[6:0] };
134
 
135
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.