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[/] [s6soc/] [trunk/] [rtl/] [memdev.v] - Blame information for rev 2

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1 2 dgisselq
module  memdev(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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                o_wb_ack, o_wb_stall, o_wb_data);
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        parameter       AW=15, DW=32;
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        input                           i_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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        input           [(AW-1):0]       i_wb_addr;
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        input           [(DW-1):0]       i_wb_data;
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        output  reg                     o_wb_ack;
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        output  wire                    o_wb_stall;
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        output  reg     [(DW-1):0]       o_wb_data;
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        reg     [(DW-1):0]       mem     [0:((1<<AW)-1)];
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        always @(posedge i_clk)
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                o_wb_data <= mem[i_wb_addr];
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        always @(posedge i_clk)
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                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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                        mem[i_wb_addr] <= i_wb_data;
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        always @(posedge i_clk)
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                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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        assign  o_wb_stall = 1'b0;
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endmodule

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