OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [memdev.v] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    memdev.v
4
//
5
// Project:     CMod S6 System on a Chip, ZipCPU demonstration Project
6
//
7
// Purpose:     This file is really simple: it creates an on-chip memory,
8
//              accessible via the wishbone bus, that can be used in this
9
//      project.  The memory has single cycle access--although getting to the
10
//      memory from the ZipCPU may cost another cycle or two in access.  Either
11
//      way, operations can be pipelined for greater speed.
12
//
13
//
14
// Creator:     Dan Gisselquist, Ph.D.
15
//              Gisselquist Technology, LLC
16
//
17
///////////////////////////////////////////////////////////////////////////
18
//
19
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
20
//
21
// This program is free software (firmware): you can redistribute it and/or
22
// modify it under the terms of  the GNU General Public License as published
23
// by the Free Software Foundation, either version 3 of the License, or (at
24
// your option) any later version.
25
//
26
// This program is distributed in the hope that it will be useful, but WITHOUT
27
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
28
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
29
// for more details.
30
//
31
// License:     GPL, v3, as defined and found on www.gnu.org,
32
//              http://www.gnu.org/licenses/gpl.html
33
//
34
//
35
///////////////////////////////////////////////////////////////////////////
36
//
37
//
38 2 dgisselq
module  memdev(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
39
                o_wb_ack, o_wb_stall, o_wb_data);
40
        parameter       AW=15, DW=32;
41
        input                           i_clk, i_wb_cyc, i_wb_stb, i_wb_we;
42
        input           [(AW-1):0]       i_wb_addr;
43
        input           [(DW-1):0]       i_wb_data;
44
        output  reg                     o_wb_ack;
45
        output  wire                    o_wb_stall;
46
        output  reg     [(DW-1):0]       o_wb_data;
47
 
48
        reg     [(DW-1):0]       mem     [0:((1<<AW)-1)];
49
        always @(posedge i_clk)
50
                o_wb_data <= mem[i_wb_addr];
51
        always @(posedge i_clk)
52
                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
53
                        mem[i_wb_addr] <= i_wb_data;
54
        always @(posedge i_clk)
55
                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
56
        assign  o_wb_stall = 1'b0;
57
 
58
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.