OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [toplevel.v] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
`timescale 10ns / 100ps
2 4 dgisselq
////////////////////////////////////////////////////////////////////////////////
3
//
4
// Filename:    toplevel.v
5
//
6
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
7
//
8
// Purpose:     This is (supposed to be) the one Xilinx specific file in the
9
//              project.  The idea is that all of the board specific logic,
10
//      the logic used in simulation, is kept in the busmaster.v  file.  It's
11
//      not quite true, since rxuart and txuart modules are instantiated here,
12
//      but it's mostly true.
13
//
14
//      One thing that makes this module unique is that all of its inputs and
15
//      outputs must match those on the chip, as specified within the cmod.ucf
16
//      file (up one directory).
17
//
18
//      Within this file you will find specific I/O for output pins, such as
19
//      the necessary adjustments to make an I2C port from GPIO pins, as well
20
//      as the clock management approach.
21
//
22
//
23
//
24
// Creator:     Dan Gisselquist, Ph.D.
25
//              Gisselquist Technology, LLC
26
//
27
////////////////////////////////////////////////////////////////////////////////
28
//
29
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
30
//
31
// This program is free software (firmware): you can redistribute it and/or
32
// modify it under the terms of  the GNU General Public License as published
33
// by the Free Software Foundation, either version 3 of the License, or (at
34
// your option) any later version.
35
//
36
// This program is distributed in the hope that it will be useful, but WITHOUT
37
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
38
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
39
// for more details.
40
//
41
// You should have received a copy of the GNU General Public License along
42
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
43
// target there if the PDF file isn't present.)  If not, see
44
// <http://www.gnu.org/licenses/> for a copy.
45
//
46
// License:     GPL, v3, as defined and found on www.gnu.org,
47
//              http://www.gnu.org/licenses/gpl.html
48
//
49
//
50
////////////////////////////////////////////////////////////////////////////////
51
//
52
//
53 2 dgisselq
module toplevel(i_clk_8mhz,
54
                o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
55
                i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
56 12 dgisselq
                        i_uart, o_uart, o_uart_cts, i_uart_rts,
57 2 dgisselq
                i_kp_row, o_kp_col,
58
                i_gpio, o_gpio,
59
                io_scl, io_sda);
60
        input           i_clk_8mhz;
61
        //
62
        // Quad SPI Flash
63
        output  wire            o_qspi_cs_n;
64
        output  wire            o_qspi_sck;
65
        inout   wire    [3:0]    io_qspi_dat;
66
        //
67
        // General purpose I/O
68
        input           [1:0]    i_btn;
69
        output  wire    [3:0]    o_led;
70
        output  wire            o_pwm, o_pwm_shutdown_n, o_pwm_gain;
71
        //
72
        // and our serial port
73
        input           i_uart;
74
        output  wire    o_uart;
75 4 dgisselq
        //      and it's associated control wires
76 12 dgisselq
        output  wire    o_uart_cts;
77
        input           i_uart_rts;
78 2 dgisselq
        // Our keypad
79
        input           [3:0]    i_kp_row;
80
        output  wire    [3:0]    o_kp_col;
81
        // and our GPIO
82
        input           [15:2]  i_gpio;
83
        output  wire    [15:2]  o_gpio;
84
        // and our I2C port
85
        inout                   io_scl, io_sda;
86
 
87
 
88 4 dgisselq
        //
89
        // Clock management
90
        //
91
        //      Generate a usable clock for the rest of the board to run at.
92
        //
93
        wire    ck_zero_0, clk_s;
94
 
95
        // Clock frequency = (20 / 2) * 8Mhz = 80 MHz
96
        // Clock period = 12.5 ns
97 2 dgisselq
        DCM_SP #(
98
                .CLKDV_DIVIDE(2.0),
99 4 dgisselq
                .CLKFX_DIVIDE(2),               // Here's the divide by two
100
                .CLKFX_MULTIPLY(20),            // and here's the multiply by 20
101 2 dgisselq
                .CLKIN_DIVIDE_BY_2("FALSE"),
102
                .CLKIN_PERIOD(125.0),
103
                .CLKOUT_PHASE_SHIFT("NONE"),
104
                .CLK_FEEDBACK("1X"),
105
                .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
106
                .DLL_FREQUENCY_MODE("LOW"),
107
                .DUTY_CYCLE_CORRECTION("TRUE"),
108
                .PHASE_SHIFT(0),
109
                .STARTUP_WAIT("TRUE")
110
        ) u0(   .CLKIN(i_clk_8mhz),
111
                .CLK0(ck_zero_0),
112
                .CLKFB(ck_zero_0),
113
                .CLKFX(clk_s),
114
                .PSEN(1'b0),
115
                .RST(1'b0));
116
 
117 4 dgisselq
        //
118 2 dgisselq
        // Generate active-high reset.
119 4 dgisselq
        //
120
        //      Actually, we don't.  Instead, let this board reset through
121
        //      the reconfiguration/power on process and we never use this
122
        //      wire.
123
        //
124 2 dgisselq
        /*
125
        reg     r_reset;
126
        initial r_reset = 1'b1;
127
        always @(posedge i_clk_12mhz)
128
                r_reset <= 1'b0;
129
        */
130
        assign  reset_s = 1'b0;
131
 
132 4 dgisselq
 
133
        //
134
        // The UART serial interface
135
        //
136
        //      Perhaps this should be part of our simulation model as well.
137
        //      For historical reasons, internal to Gisselquist Technology,
138
        //      this has remained separate from the simulation, allowing the
139
        //      simulation to bypass whether or not these two functions work.
140
        //
141 2 dgisselq
        wire            rx_stb, tx_stb;
142
        wire    [7:0]    rx_data, tx_data;
143
        wire            tx_busy;
144
        wire    [29:0]   uart_setup;
145
 
146
        wire    rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
147
        assign  tx_break = 1'b0;
148 4 dgisselq
        rxuart  rcvuart(clk_s, reset_s, uart_setup,
149
                        i_uart, rx_stb, rx_data,
150 2 dgisselq
                        rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
151
        txuart  tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
152 12 dgisselq
                        o_uart, tx_busy);
153 2 dgisselq
 
154
 
155 4 dgisselq
        //
156
        // BUSMASTER
157
        //
158
        //      Busmaster is so named because it contains the wishbone
159
        //      interconnect that all of the internal devices are hung off of.
160
        //      To reconfigure this device for another purpose, usually
161
        //      the busmaster module (i.e. the interconnect) is all that needs
162
        //      to be changed: either to add more devices, or to remove them.
163
        //
164 2 dgisselq
        wire    [3:0]    qspi_dat;
165
        wire    [1:0]    qspi_bmod;
166
        wire    [15:0]   w_gpio;
167
 
168
        busmaster       masterbus(clk_s, reset_s,
169
                // External ... bus control (if enabled)
170 12 dgisselq
                rx_stb, rx_data, tx_stb, tx_data, tx_busy, w_uart_cts,
171 2 dgisselq
                // SPI/SD-card flash
172
                o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
173
                // Board lights and switches
174
                i_btn, o_led, o_pwm, { o_pwm_shutdown_n, o_pwm_gain },
175
                // Keypad connections
176
                i_kp_row, o_kp_col,
177
                // UART control
178
                uart_setup,
179
                // GPIO lines
180
                { i_gpio, io_scl, io_sda }, w_gpio
181
                );
182 12 dgisselq
        assign  o_uart_cts = (w_uart_cts)&&(i_uart_rts);
183 2 dgisselq
 
184 4 dgisselq
        //
185
        // Quad SPI support
186
        //
187
        //      Supporting a Quad SPI port requires knowing which direction the
188
        //      wires are going at each instant, whether the device is in full
189
        //      Quad mode in, full quad mode out, or simply the normal SPI
190
        //      port with one wire in and one wire out.  This utilizes our
191
        //      control wires (qspi_bmod) to set the output lines appropriately.
192
        //
193 2 dgisselq
        assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
194
                                :((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
195
 
196 4 dgisselq
        //
197
        // I2C support
198
        //
199
        //      Supporting I2C requires a couple quick adjustments to our
200
        //      GPIO lines.  Specifically, we'll allow that when the output
201
        //      (i.e. w_gpio) pins are high, then the I2C lines float.  They
202
        //      will be (need to be) pulled up by a resistor in order to 
203
        //      match the I2C protocol, but this change makes them look/act
204
        //      more like GPIO pins.
205
        //
206 2 dgisselq
        assign  io_sda = (w_gpio[0]) ? 1'bz : 1'b0;
207
        assign  io_scl = (w_gpio[1]) ? 1'bz : 1'b0;
208
        assign  o_gpio[15:2] = w_gpio[15:2];
209
 
210
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.