OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [txuartlite.v] - Blame information for rev 51

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 51 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    txuartlite.v
4
//
5
// Project:     wbuart32, a full featured UART with simulator
6
//
7
// Purpose:     Transmit outputs over a single UART line.  This particular UART
8
//              implementation has been extremely simplified: it does not handle
9
//      generating break conditions, nor does it handle anything other than the
10
//      8N1 (8 data bits, no parity, 1 stop bit) UART sub-protocol.
11
//
12
//      To interface with this module, connect it to your system clock, and
13
//      pass it the byte of data you wish to transmit.  Strobe the i_wr line
14
//      high for one cycle, and your data will be off.  Wait until the 'o_busy'
15
//      line is low before strobing the i_wr line again--this implementation
16
//      has NO BUFFER, so strobing i_wr while the core is busy will just
17
//      get ignored.  The output will be placed on the o_txuart output line. 
18
//
19
//      (I often set both data and strobe on the same clock, and then just leave
20
//      them set until the busy line is low.  Then I move on to the next piece
21
//      of data.)
22
//
23
// Creator:     Dan Gisselquist, Ph.D.
24
//              Gisselquist Technology, LLC
25
//
26
////////////////////////////////////////////////////////////////////////////////
27
//
28
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
29
//
30
// This program is free software (firmware): you can redistribute it and/or
31
// modify it under the terms of  the GNU General Public License as published
32
// by the Free Software Foundation, either version 3 of the License, or (at
33
// your option) any later version.
34
//
35
// This program is distributed in the hope that it will be useful, but WITHOUT
36
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
37
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
38
// for more details.
39
//
40
// You should have received a copy of the GNU General Public License along
41
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
42
// target there if the PDF file isn't present.)  If not, see
43
// <http://www.gnu.org/licenses/> for a copy.
44
//
45
// License:     GPL, v3, as defined and found on www.gnu.org,
46
//              http://www.gnu.org/licenses/gpl.html
47
//
48
//
49
////////////////////////////////////////////////////////////////////////////////
50
//
51
//
52
`define TXU_BIT_ZERO    4'h0
53
`define TXU_BIT_ONE     4'h1
54
`define TXU_BIT_TWO     4'h2
55
`define TXU_BIT_THREE   4'h3
56
`define TXU_BIT_FOUR    4'h4
57
`define TXU_BIT_FIVE    4'h5
58
`define TXU_BIT_SIX     4'h6
59
`define TXU_BIT_SEVEN   4'h7
60
`define TXU_STOP        4'h8
61
`define TXU_IDLE        4'hf
62
//
63
//
64
module txuartlite(i_clk, i_wr, i_data, o_uart_tx, o_busy);
65
        parameter       [23:0]   CLOCKS_PER_BAUD = 24'd868;
66
        input                   i_clk;
67
        input                   i_wr;
68
        input           [7:0]    i_data;
69
        // And the UART input line itself
70
        output  reg             o_uart_tx;
71
        // A line to tell others when we are ready to accept data.  If
72
        // (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
73
        // for transmission.
74
        output  wire            o_busy;
75
 
76
        reg     [23:0]   baud_counter;
77
        reg     [3:0]    state;
78
        reg     [7:0]    lcl_data;
79
        reg             r_busy, zero_baud_counter;
80
 
81
        initial r_busy = 1'b1;
82
        initial state  = `TXU_IDLE;
83
        initial lcl_data= 8'h0;
84
        always @(posedge i_clk)
85
        begin
86
                if (!zero_baud_counter)
87
                        // r_busy needs to be set coming into here
88
                        r_busy <= 1'b1;
89
                else if (state == `TXU_IDLE)    // STATE_IDLE
90
                begin
91
                        r_busy <= 1'b0;
92
                        if ((i_wr)&&(!r_busy))
93
                        begin   // Immediately start us off with a start bit
94
                                r_busy <= 1'b1;
95
                                state <= `TXU_BIT_ZERO;
96
                        end
97
                end else begin
98
                        // One clock tick in each of these states ...
99
                        r_busy <= 1'b1;
100
                        if (state <=`TXU_STOP) // start bit, 8-d bits, stop-b
101
                                state <= state + 1;
102
                        else
103
                                state <= `TXU_IDLE;
104
                end
105
        end
106
 
107
        // o_busy
108
        //
109
        // This is a wire, designed to be true is we are ever busy above.
110
        // originally, this was going to be true if we were ever not in the
111
        // idle state.  The logic has since become more complex, hence we have
112
        // a register dedicated to this and just copy out that registers value.
113
        assign  o_busy = (r_busy);
114
 
115
 
116
        // lcl_data
117
        //
118
        // This is our working copy of the i_data register which we use
119
        // when transmitting.  It is only of interest during transmit, and is
120
        // allowed to be whatever at any other time.  Hence, if r_busy isn't
121
        // true, we can always set it.  On the one clock where r_busy isn't
122
        // true and i_wr is, we set it and r_busy is true thereafter.
123
        // Then, on any zero_baud_counter (i.e. change between baud intervals)
124
        // we simple logically shift the register right to grab the next bit.
125
        initial lcl_data = 8'hff;
126
        always @(posedge i_clk)
127
                if ((i_wr)&&(!r_busy))
128
                        lcl_data <= i_data;
129
                else if (zero_baud_counter)
130
                        lcl_data <= { 1'b1, lcl_data[7:1] };
131
 
132
        // o_uart_tx
133
        //
134
        // This is the final result/output desired of this core.  It's all
135
        // centered about o_uart_tx.  This is what finally needs to follow
136
        // the UART protocol.
137
        //
138
        initial o_uart_tx = 1'b1;
139
        always @(posedge i_clk)
140
                if ((i_wr)&&(!r_busy))
141
                        o_uart_tx <= 1'b0;      // Set the start bit on writes
142
                else if (zero_baud_counter)     // Set the data bit.
143
                        o_uart_tx <= lcl_data[0];
144
 
145
 
146
        // All of the above logic is driven by the baud counter.  Bits must last
147
        // CLOCKS_PER_BAUD in length, and this baud counter is what we use to
148
        // make certain of that.
149
        //
150
        // The basic logic is this: at the beginning of a bit interval, start
151
        // the baud counter and set it to count CLOCKS_PER_BAUD.  When it gets
152
        // to zero, restart it.
153
        //
154
        // However, comparing a 28'bit number to zero can be rather complex--
155
        // especially if we wish to do anything else on that same clock.  For
156
        // that reason, we create "zero_baud_counter".  zero_baud_counter is
157
        // nothing more than a flag that is true anytime baud_counter is zero.
158
        // It's true when the logic (above) needs to step to the next bit.
159
        // Simple enough?
160
        //
161
        // I wish we could stop there, but there are some other (ugly)
162
        // conditions to deal with that offer exceptions to this basic logic.
163
        //
164
        // 1. When the user has commanded a BREAK across the line, we need to
165
        // wait several baud intervals following the break before we start
166
        // transmitting, to give any receiver a chance to recognize that we are
167
        // out of the break condition, and to know that the next bit will be
168
        // a stop bit.
169
        //
170
        // 2. A reset is similar to a break condition--on both we wait several
171
        // baud intervals before allowing a start bit.
172
        //
173
        // 3. In the idle state, we stop our counter--so that upon a request
174
        // to transmit when idle we can start transmitting immediately, rather
175
        // than waiting for the end of the next (fictitious and arbitrary) baud
176
        // interval.
177
        //
178
        // When (i_wr)&&(!r_busy)&&(state == `TXU_IDLE) then we're not only in
179
        // the idle state, but we also just accepted a command to start writing
180
        // the next word.  At this point, the baud counter needs to be reset
181
        // to the number of CLOCKS_PER_BAUD, and zero_baud_counter set to zero.
182
        //
183
        // The logic is a bit twisted here, in that it will only check for the
184
        // above condition when zero_baud_counter is false--so as to make
185
        // certain the STOP bit is complete.
186
        initial zero_baud_counter = 1'b0;
187
        initial baud_counter = 24'h05;
188
        always @(posedge i_clk)
189
        begin
190
                zero_baud_counter <= (baud_counter == 24'h01);
191
                if (state == `TXU_IDLE)
192
                begin
193
                        baud_counter <= 24'h0;
194
                        zero_baud_counter <= 1'b1;
195
                        if ((i_wr)&&(!r_busy))
196
                        begin
197
                                baud_counter <= CLOCKS_PER_BAUD - 24'h01;
198
                                zero_baud_counter <= 1'b0;
199
                        end
200
                end else if (!zero_baud_counter)
201
                        baud_counter <= baud_counter - 24'h01;
202
                else
203
                        baud_counter <= CLOCKS_PER_BAUD - 24'h01;
204
        end
205
endmodule
206
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.