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[/] [s6soc/] [trunk/] [rtl/] [wbqspiflash.v] - Blame information for rev 46

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1 46 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3
// Filename:    wbspiflash.v
4
//
5 46 dgisselq
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6 2 dgisselq
//
7
// Purpose:     Access a Quad SPI flash via a WISHBONE interface.  This
8
//              includes both read and write (and erase) commands to the SPI
9
//              flash.  All read/write commands are accomplished using the
10
//              high speed (4-bit) interface.  Further, the device will be
11
//              left/kept in the 4-bit read interface mode between accesses,
12
//              for a minimum read latency.
13
//
14
//      Wishbone Registers (See spec sheet for more detail):
15
//      0: local config(r) / erase commands(w) / deep power down cmds / etc.
16
//      R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
17
//              { last_erased_sector, 14'h00 } if (WIP)
18
//              else { current_sector_being_erased, 14'h00 }
19
//              current if write in progress, last if written
20
//      W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
21
//      1: Configuration register
22
//      2: Status register (R/w)
23
//      3: Read ID (read only)
24
//      (19 bits): Data (R/w, but expect writes to take a while)
25
//              
26
//
27 46 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
28 2 dgisselq
//              Gisselquist Technology, LLC
29
//
30 46 dgisselq
////////////////////////////////////////////////////////////////////////////////
31 2 dgisselq
//
32 46 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
33 2 dgisselq
//
34
// This program is free software (firmware): you can redistribute it and/or
35
// modify it under the terms of  the GNU General Public License as published
36
// by the Free Software Foundation, either version 3 of the License, or (at
37
// your option) any later version.
38
//
39
// This program is distributed in the hope that it will be useful, but WITHOUT
40
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
41
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
42
// for more details.
43
//
44
// You should have received a copy of the GNU General Public License along
45 46 dgisselq
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
46 2 dgisselq
// target there if the PDF file isn't present.)  If not, see
47
// <http://www.gnu.org/licenses/> for a copy.
48
//
49
// License:     GPL, v3, as defined and found on www.gnu.org,
50
//              http://www.gnu.org/licenses/gpl.html
51
//
52
//
53 46 dgisselq
////////////////////////////////////////////////////////////////////////////////
54 2 dgisselq
//
55 46 dgisselq
//
56 8 dgisselq
`include "flashconfig.v"
57 2 dgisselq
//
58
`define WBQSPI_RESET            0
59
`define WBQSPI_RESET_QUADMODE   1
60
`define WBQSPI_IDLE             2
61
`define WBQSPI_RDIDLE           3       // Idle, but in fast read mode
62
`define WBQSPI_WBDECODE         4
63
`define WBQSPI_RD_DUMMY         5
64
`define WBQSPI_QRD_ADDRESS      6
65
`define WBQSPI_QRD_DUMMY        7
66
`define WBQSPI_READ_CMD         8
67
`define WBQSPI_READ_DATA        9
68
`define WBQSPI_WAIT_TIL_RDIDLE  10
69 46 dgisselq
`define WBQSPI_READ_ID_CMD      11
70
`define WBQSPI_READ_ID          12
71
`define WBQSPI_READ_STATUS      13
72
`define WBQSPI_READ_CONFIG      14
73 2 dgisselq
`define WBQSPI_WAIT_TIL_IDLE    15
74
//
75
//
76
`ifndef READ_ONLY
77
//
78
`define WBQSPI_WAIT_WIP_CLEAR   16
79
`define WBQSPI_CHECK_WIP_CLEAR  17
80
`define WBQSPI_CHECK_WIP_DONE   18
81
`define WBQSPI_WEN              19
82
`define WBQSPI_PP               20      // Program page
83
`define WBQSPI_QPP              21      // Program page, 4 bit mode
84
`define WBQSPI_WR_DATA          22
85
`define WBQSPI_WR_BUS_CYCLE     23
86
`define WBQSPI_WRITE_STATUS     24
87
`define WBQSPI_WRITE_CONFIG     25
88
`define WBQSPI_ERASE_WEN        26
89
`define WBQSPI_ERASE_CMD        27
90
`define WBQSPI_ERASE_BLOCK      28
91
`define WBQSPI_CLEAR_STATUS     29
92
`define WBQSPI_IDLE_CHECK_WIP   30
93
//
94
`endif
95
 
96
module  wbqspiflash(i_clk_100mhz,
97
                // Internal wishbone connections
98
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
99
                i_wb_addr, i_wb_data,
100
                // Wishbone return values
101
                o_wb_ack, o_wb_stall, o_wb_data,
102
                // Quad Spi connections to the external device
103
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
104
                o_interrupt);
105
        parameter       ADDRESS_WIDTH=22;
106 46 dgisselq
        localparam      AW = ADDRESS_WIDTH-2;
107 2 dgisselq
        input                   i_clk_100mhz;
108
        // Wishbone, inputs first
109
        input                   i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
110 46 dgisselq
        input           [(AW-1):0]       i_wb_addr;
111 2 dgisselq
        input           [31:0]   i_wb_data;
112
        // then outputs
113
        output  reg             o_wb_ack;
114
        output  reg             o_wb_stall;
115
        output  reg     [31:0]   o_wb_data;
116
        // Quad SPI control wires
117
        output  wire            o_qspi_sck, o_qspi_cs_n;
118
        output  wire    [1:0]    o_qspi_mod;
119
        output  wire    [3:0]    o_qspi_dat;
120
        input           [3:0]    i_qspi_dat;
121
        // Interrupt line
122
        output  reg             o_interrupt;
123
        // output       wire    [31:0]  o_debug;
124
 
125
        reg             spi_wr, spi_hold, spi_spd, spi_dir;
126
        reg     [31:0]   spi_in;
127
        reg     [1:0]    spi_len;
128
        wire    [31:0]   spi_out;
129
        wire            spi_valid, spi_busy;
130
        wire            w_qspi_sck, w_qspi_cs_n;
131
        wire    [3:0]    w_qspi_dat;
132
        wire    [1:0]    w_qspi_mod;
133
        // wire [22:0]  spi_dbg;
134
        llqspi  lldriver(i_clk_100mhz,
135
                        spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
136
                                spi_out, spi_valid, spi_busy,
137
                        w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
138
                                i_qspi_dat);
139
 
140
        // Erase status tracking
141
        reg             write_in_progress, write_protect;
142
        reg     [(ADDRESS_WIDTH-17):0]   erased_sector;
143
        reg             dirty_sector;
144
        initial begin
145
                write_in_progress = 1'b0;
146
                erased_sector = 0;
147
                dirty_sector  = 1'b1;
148
                write_protect = 1'b1;
149
        end
150
 
151
        reg     [7:0]    last_status;
152 11 dgisselq
        reg     [9:0]    reset_counter;
153 2 dgisselq
        reg             quad_mode_enabled;
154
        reg             spif_cmd, spif_override;
155 46 dgisselq
        reg     [(AW-1):0]       spif_addr;
156 2 dgisselq
        reg     [31:0]   spif_data;
157
        reg     [5:0]    state;
158
        reg             spif_ctrl, spif_req;
159 11 dgisselq
        reg             alt_cmd, alt_ctrl;
160 2 dgisselq
        wire    [(ADDRESS_WIDTH-17):0]   spif_sector;
161 46 dgisselq
        assign  spif_sector = spif_addr[(AW-1):14];
162 2 dgisselq
 
163
        // assign       o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
164
 
165
        initial state = `WBQSPI_RESET;
166
        initial o_wb_ack   = 1'b0;
167
        initial o_wb_stall = 1'b1;
168
        initial spi_wr     = 1'b0;
169
        initial spi_len    = 2'b00;
170
        initial quad_mode_enabled = 1'b0;
171
        initial o_interrupt = 1'b0;
172 11 dgisselq
        initial spif_override = 1'b1;
173 46 dgisselq
        initial spif_ctrl     = 1'b0;
174 2 dgisselq
        always @(posedge i_clk_100mhz)
175
        begin
176
        spif_override <= 1'b0;
177 11 dgisselq
        alt_cmd  <= (reset_counter[9:8]==2'b10)?reset_counter[3]:1'b1; // Toggle CS_n
178
        alt_ctrl <= (reset_counter[9:8]==2'b10)?reset_counter[0]:1'b1; // Toggle clock too
179 2 dgisselq
        if (state == `WBQSPI_RESET)
180
        begin
181
                // From a reset, we should
182
                //      Enable the Quad I/O mode
183
                //      Disable the Write protection bits in the status register
184
                //      Chip should already be up and running, so we can start
185
                //      immediately ....
186
                o_wb_ack <= 1'b0;
187
                o_wb_stall <= 1'b1;
188
                spi_wr   <= 1'b0;
189
                spi_hold <= 1'b0;
190
                spi_spd  <= 1'b0;
191
                spi_dir  <= 1'b0;
192
                last_status <= 8'h00;
193
                state <= `WBQSPI_RESET_QUADMODE;
194
                spif_req <= 1'b0;
195
                spif_override <= 1'b1;
196 11 dgisselq
                last_status   <= 8'h00; //
197
                reset_counter <= 10'h3fc; //
198 2 dgisselq
                        // This guarantees that we aren't starting in quad
199
                        // I/O mode, where the FPGA configuration scripts may
200
                        // have left us.
201
        end else if (state == `WBQSPI_RESET_QUADMODE)
202
        begin
203
                // Okay, so here's the problem: we don't know whether or not
204
                // the Xilinx loader started us up in Quad Read I/O idle mode.
205 11 dgisselq
                // So, thus we need to toggle the clock and CS_n, with fewer
206
                // clocks than are necessary to transmit a word.
207
                //
208 2 dgisselq
                // Not ready to handle the bus yet, so stall any requests
209
                o_wb_ack   <= 1'b0;
210
                o_wb_stall <= 1'b1;
211
 
212
                // Do something ...
213 11 dgisselq
                if (reset_counter == 10'h00)
214 2 dgisselq
                begin
215
                        spif_override <= 1'b0;
216
                        state <= `WBQSPI_IDLE;
217 11 dgisselq
 
218
                        // Find out if we can use Quad I/O mode ...
219
                        state <= `WBQSPI_READ_CONFIG;
220
                        spi_wr <= 1'b1;
221
                        spi_len <= 2'b01;
222
                        spi_in <= { 8'h35, 24'h00};
223
 
224 2 dgisselq
                end else begin
225 11 dgisselq
                        reset_counter <= reset_counter - 10'h1;
226 2 dgisselq
                        spif_override <= 1'b1;
227
                end
228
        end else if (state == `WBQSPI_IDLE)
229
        begin
230
                o_interrupt <= 1'b0;
231
                o_wb_stall <= 1'b0;
232
                o_wb_ack <= 1'b0;
233
                spif_cmd   <= i_wb_we;
234
                spif_addr  <= i_wb_addr;
235
                spif_data  <= i_wb_data;
236
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
237
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
238
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
239
                spi_hold <= 1'b0;
240
                spi_spd  <= 1'b0;
241
                spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
242
                // Data register access
243 46 dgisselq
                if (i_wb_data_stb)
244 2 dgisselq
                begin
245
 
246
                        if (i_wb_we) // Request to write a page
247
                        begin
248
`ifdef  READ_ONLY
249
                                o_wb_ack <= 1'b1;
250
                                o_wb_stall <= 1'b0;
251
                        end else
252
`else
253
                                if((~write_protect)&&(~write_in_progress))
254
                                begin // 00
255
                                        spi_wr <= 1'b1;
256
                                        spi_len <= 2'b00; // 8 bits
257
                                        // Send a write enable command
258
                                        spi_in <= { 8'h06, 24'h00 };
259
                                        state <= `WBQSPI_WEN;
260
 
261
                                        o_wb_ack <= 1'b0;
262
                                        o_wb_stall <= 1'b1;
263
                                end else if (write_protect)
264
                                begin // whether or not write-in_progress ...
265
                                        // Do nothing on a write protect
266
                                        // violation
267
                                        //
268
                                        o_wb_ack <= 1'b1;
269
                                        o_wb_stall <= 1'b0;
270
                                end else begin // write is in progress, wait
271
                                        // for it to complete
272
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
273
                                        o_wb_ack <= 1'b0;
274
                                        o_wb_stall <= 1'b1;
275
                                end
276
                        end else if (~write_in_progress)
277
`endif
278
                        begin // Read access, normal mode(s)
279
                                o_wb_ack   <= 1'b0;
280
                                o_wb_stall <= 1'b1;
281
                                spi_wr     <= 1'b1;     // Write cmd to device
282
                                if (quad_mode_enabled)
283
                                begin
284
                                        spi_in <= { 8'heb,
285
                                                {(24-ADDRESS_WIDTH){1'b0}},
286 46 dgisselq
                                                i_wb_addr[(AW-1):0], 2'b00 };
287 2 dgisselq
                                        state <= `WBQSPI_QRD_ADDRESS;
288
                                        spi_len    <= 2'b00; // single byte, cmd only
289
                                end else begin
290
                                        spi_in <= { 8'h0b,
291
                                                {(24-ADDRESS_WIDTH){1'b0}},
292 46 dgisselq
                                                i_wb_addr[(AW-1):0], 2'b00 };
293 2 dgisselq
                                        state <= `WBQSPI_RD_DUMMY;
294
                                        spi_len    <= 2'b11; // cmd+addr,32bits
295
                                end
296
`ifndef READ_ONLY
297
                        end else begin
298
                                // A write is in progress ... need to stall
299
                                // the bus until the write is complete.
300
                                state <= `WBQSPI_WAIT_WIP_CLEAR;
301
                                o_wb_ack   <= 1'b0;
302
                                o_wb_stall <= 1'b1;
303
`endif
304
                        end
305 46 dgisselq
                end else if ((i_wb_ctrl_stb)&&(i_wb_we))
306 2 dgisselq
                begin
307
`ifdef  READ_ONLY
308
                        o_wb_ack   <= 1'b1;
309
                        o_wb_stall <= 1'b0;
310
`else
311
                        o_wb_stall <= 1'b1;
312
                        case(i_wb_addr[1:0])
313
                        2'b00: begin // Erase command register
314
                                write_protect <= ~i_wb_data[28];
315
                                o_wb_stall <= 1'b0;
316
 
317
                                if((i_wb_data[31])&&(~write_in_progress))
318
                                begin
319
                                        // Command an erase--ack it immediately
320
 
321
                                        o_wb_ack <= 1'b1;
322
                                        o_wb_stall <= 1'b0;
323
 
324
                                        if ((i_wb_data[31])&&(~write_protect))
325
                                        begin
326
                                                spi_wr <= 1'b1;
327
                                                spi_len <= 2'b00;
328
                                                // Send a write enable command
329
                                                spi_in <= { 8'h06, 24'h00 };
330
                                                state <= `WBQSPI_ERASE_CMD;
331
                                                o_wb_stall <= 1'b1;
332
                                        end
333
                                end else if (i_wb_data[31])
334
                                begin
335
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
336
                                        o_wb_ack   <= 1'b1;
337
                                        o_wb_stall <= 1'b1;
338
                                end else
339
                                        o_wb_ack   <= 1'b1;
340
                                        o_wb_stall <= 1'b0;
341
                                end
342
                        2'b01: begin
343
                                // Write the configuration register
344
                                o_wb_ack <= 1'b1;
345
                                o_wb_stall <= 1'b1;
346
 
347
                                // Need to send a write enable command first
348
                                spi_wr <= 1'b1;
349
                                spi_len <= 2'b00; // 8 bits
350
                                // Send a write enable command
351
                                spi_in <= { 8'h06, 24'h00 };
352
                                state <= `WBQSPI_WRITE_CONFIG;
353
                                end
354
                        2'b10: begin
355
                                // Write the status register
356
                                o_wb_ack <= 1'b1; // Ack immediately
357
                                o_wb_stall <= 1'b1; // Stall other cmds
358
                                // Need to send a write enable command first
359
                                spi_wr <= 1'b1;
360
                                spi_len <= 2'b00; // 8 bits
361
                                // Send a write enable command
362
                                spi_in <= { 8'h06, 24'h00 };
363
                                state <= `WBQSPI_WRITE_STATUS;
364
                                end
365
                        2'b11: begin // Write the ID register??? makes no sense
366
                                o_wb_ack <= 1'b1;
367
                                o_wb_stall <= 1'b0;
368
                                end
369
                        endcase
370
`endif
371 46 dgisselq
                end else if (i_wb_ctrl_stb) // &&(~i_wb_we))
372 2 dgisselq
                begin
373
                        case(i_wb_addr[1:0])
374
                        2'b00: begin // Read local register
375
                                if (write_in_progress) // Read status
376
                                begin// register, is write still in progress?
377
                                        state <= `WBQSPI_READ_STATUS;
378
                                        spi_wr <= 1'b1;
379
                                        spi_len <= 2'b01;// 8 bits out, 8 bits in
380
                                        spi_in <= { 8'h05, 24'h00};
381
 
382
                                        o_wb_ack <= 1'b0;
383
                                        o_wb_stall <= 1'b1;
384
                                end else begin // Return w/o talking to device
385
                                        o_wb_ack <= 1'b1;
386
                                        o_wb_stall <= 1'b0;
387
                                        o_wb_data <= { write_in_progress,
388
                                                dirty_sector, spi_busy,
389
                                                ~write_protect,
390
                                                quad_mode_enabled,
391
                                                {(29-ADDRESS_WIDTH){1'b0}},
392
                                                erased_sector, 14'h000 };
393
                                end end
394
                        2'b01: begin // Read configuration register
395
                                state <= `WBQSPI_READ_CONFIG;
396
                                spi_wr <= 1'b1;
397
                                spi_len <= 2'b01;
398
                                spi_in <= { 8'h35, 24'h00};
399
 
400
                                o_wb_ack <= 1'b0;
401
                                o_wb_stall <= 1'b1;
402
                                end
403
                        2'b10: begin // Read status register
404
                                state <= `WBQSPI_READ_STATUS;
405
                                spi_wr <= 1'b1;
406
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
407
                                spi_in <= { 8'h05, 24'h00};
408
 
409
                                o_wb_ack <= 1'b0;
410
                                o_wb_stall <= 1'b1;
411
                                end
412
                        2'b11: begin // Read ID register
413
                                state <= `WBQSPI_READ_ID_CMD;
414
                                spi_wr <= 1'b1;
415
                                spi_len <= 2'b00;
416
                                spi_in <= { 8'h9f, 24'h00};
417
 
418
                                o_wb_ack <= 1'b0;
419
                                o_wb_stall <= 1'b1;
420
                                end
421
                        endcase
422
`ifndef READ_ONLY
423
                end else if ((~i_wb_cyc)&&(write_in_progress))
424
                begin
425
                        state <= `WBQSPI_IDLE_CHECK_WIP;
426
                        spi_wr <= 1'b1;
427
                        spi_len <= 2'b01; // 8 bits out, 8 bits in
428
                        spi_in <= { 8'h05, 24'h00};
429
 
430
                        o_wb_ack <= 1'b0;
431
                        o_wb_stall <= 1'b1;
432
`endif
433
                end
434
        end else if (state == `WBQSPI_RDIDLE)
435
        begin
436
                spi_wr <= 1'b0;
437
                o_wb_stall <= 1'b0;
438
                o_wb_ack <= 1'b0;
439
                spif_cmd   <= i_wb_we;
440
                spif_addr  <= i_wb_addr;
441
                spif_data  <= i_wb_data;
442
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
443
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
444
                spi_hold <= 1'b0;
445
                spi_spd<= 1'b1;
446
                spi_dir <= 1'b0; // Write (for now)
447 46 dgisselq
                if ((i_wb_data_stb)&&(~i_wb_we))
448 2 dgisselq
                begin // Continue our read ... send the new address / mode
449
                        o_wb_stall <= 1'b1;
450
                        spi_wr <= 1'b1;
451
                        spi_len <= 2'b10; // Write address, but not mode byte
452
                        spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
453 46 dgisselq
                                        i_wb_addr[(AW-1):0], 2'b00, 8'ha0 };
454 2 dgisselq
                        state <= `WBQSPI_QRD_DUMMY;
455 46 dgisselq
                end else if((i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
456 2 dgisselq
                begin
457
                        // A local read that doesn't touch the device, so leave
458
                        // the device in its current state
459
                        o_wb_stall <= 1'b0;
460
                        o_wb_ack <= 1'b1;
461
                        o_wb_data <= { write_in_progress,
462
                                        dirty_sector, spi_busy,
463
                                        ~write_protect,
464
                                        quad_mode_enabled,
465
                                        {(29-ADDRESS_WIDTH){1'b0}},
466
                                        erased_sector, 14'h000 };
467 46 dgisselq
                end else if(((i_wb_ctrl_stb)||(i_wb_data_stb)))
468 2 dgisselq
                begin // Need to release the device from quad mode for all else
469
                        o_wb_ack   <= 1'b0;
470
                        o_wb_stall <= 1'b1;
471
                        spi_wr <= 1'b1;
472
                        spi_len <= 2'b11;
473
                        spi_in <= 32'h00;
474
                        state <= `WBQSPI_WBDECODE;
475
                end
476
        end else if (state == `WBQSPI_WBDECODE)
477
        begin
478
                // We were in quad SPI read mode, and had to get out.
479
                // Now we've got a command (not data read) to read and
480
                // execute.  Accomplish what we would've done while in the
481
                // IDLE state here, save only that we don't have to worry
482
                // about data reads, and we need to operate on a stored
483
                // version of the bus command
484
                o_wb_stall <= 1'b1;
485
                o_wb_ack <= 1'b0;
486
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
487
                spi_hold <= 1'b0;
488
                spi_spd <= 1'b0;
489
                spi_dir <= 1'b0;
490
                spif_req<= (spif_req) && (i_wb_cyc);
491
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
492
                begin
493
                        // Data register access
494
                        if (~spif_ctrl)
495
                        begin
496
                                if (spif_cmd) // Request to write a page
497
                                begin
498
`ifdef  READ_ONLY
499
                                        o_wb_ack <= spif_req;
500
                                        o_wb_stall <= 1'b0;
501
                                        state <= `WBQSPI_IDLE;
502
`else
503
                                        if((~write_protect)&&(~write_in_progress))
504
                                        begin // 00
505
                                                spi_wr <= 1'b1;
506
                                                spi_len <= 2'b00; // 8 bits
507
                                                // Send a write enable command
508
                                                spi_in <= { 8'h06, 24'h00 };
509
                                                state <= `WBQSPI_WEN;
510
 
511
                                                o_wb_ack <= 1'b0;
512
                                                o_wb_stall <= 1'b1;
513
                                        end else if (write_protect)
514
                                        begin // whether or not write-in_progress ...
515
                                                // Do nothing on a write protect
516
                                                // violation
517
                                                //
518
                                                o_wb_ack <= spif_req;
519
                                                o_wb_stall <= 1'b0;
520
                                                state <= `WBQSPI_IDLE;
521
                                        end else begin // write is in progress, wait
522
                                                // for it to complete
523
                                                state <= `WBQSPI_WAIT_WIP_CLEAR;
524
                                                o_wb_ack <= 1'b0;
525
                                                o_wb_stall <= 1'b1;
526
                                        end
527
                                // end else if (~write_in_progress) // always true
528
                                // but ... we wouldn't get here on a normal read access
529
`endif
530
                                end else begin
531
                                        // Something's wrong, we should never
532
                                        //   get here
533
                                        // Attempt to go to idle to recover
534
                                        state <= `WBQSPI_IDLE;
535
                                end
536
                        end else if ((spif_ctrl)&&(spif_cmd))
537
                        begin
538
`ifdef  READ_ONLY
539
                                o_wb_ack   <= spif_req;
540
                                o_wb_stall <= 1'b0;
541
                                state <= `WBQSPI_IDLE;
542
`else
543
                                o_wb_stall <= 1'b1;
544
                                case(spif_addr[1:0])
545
                                2'b00: begin // Erase command register
546
                                        o_wb_ack   <= spif_req;
547
                                        o_wb_stall <= 1'b0;
548
                                        state <= `WBQSPI_IDLE;
549
                                        write_protect <= ~spif_data[28];
550
                                        // Are we commanding an erase?
551
                                        // We're in read mode, writes cannot
552
                                        // be in progress, so ...
553
                                        if (spif_data[31]) // Command an erase
554
                                        begin
555
                                                // Since we're not going back
556
                                                // to IDLE, we must stall the
557
                                                // bus here
558
                                                o_wb_stall <= 1'b1;
559
                                                spi_wr <= 1'b1;
560
                                                spi_len <= 2'b00;
561
                                                // Send a write enable command
562
                                                spi_in <= { 8'h06, 24'h00 };
563
                                                state <= `WBQSPI_ERASE_CMD;
564
                                        end end
565
                                2'b01: begin
566
                                        // Write the configuration register
567
                                        o_wb_ack <= spif_req;
568
                                        o_wb_stall <= 1'b1;
569
 
570
                                        // Need to send a write enable command first
571
                                        spi_wr <= 1'b1;
572
                                        spi_len <= 2'b00; // 8 bits
573
                                        // Send a write enable command
574
                                        spi_in <= { 8'h06, 24'h00 };
575
                                        state <= `WBQSPI_WRITE_CONFIG;
576
                                        end
577
                                2'b10: begin
578
                                        // Write the status register
579
                                        o_wb_ack <= spif_req; // Ack immediately
580
                                        o_wb_stall <= 1'b1; // Stall other cmds
581
                                        // Need to send a write enable command first
582
                                        spi_wr <= 1'b1;
583
                                        spi_len <= 2'b00; // 8 bits
584
                                        // Send a write enable command
585
                                        spi_in <= { 8'h06, 24'h00 };
586
                                        state <= `WBQSPI_WRITE_STATUS;
587
                                        end
588
                                2'b11: begin // Write the ID register??? makes no sense
589
                                        o_wb_ack <= spif_req;
590
                                        o_wb_stall <= 1'b0;
591
                                        state <= `WBQSPI_IDLE;
592
                                        end
593
                                endcase
594
`endif
595
                        end else begin // on (~spif_we)
596
                                case(spif_addr[1:0])
597
                                2'b00: begin // Read local register
598
                                        // Nonsense case--would've done this
599
                                        // already
600
                                        state <= `WBQSPI_IDLE;
601
                                        o_wb_ack <= spif_req;
602
                                        o_wb_stall <= 1'b0;
603
                                        end
604
                                2'b01: begin // Read configuration register
605
                                        state <= `WBQSPI_READ_CONFIG;
606
                                        spi_wr <= 1'b1;
607
                                        spi_len <= 2'b01;
608
                                        spi_in <= { 8'h35, 24'h00};
609
 
610
                                        o_wb_ack <= 1'b0;
611
                                        o_wb_stall <= 1'b1;
612
                                        end
613
                                2'b10: begin // Read status register
614
                                        state <= `WBQSPI_READ_STATUS;
615
                                        spi_wr <= 1'b1;
616
                                        spi_len <= 2'b01; // 8 bits out, 8 bits in
617
                                        spi_in <= { 8'h05, 24'h00};
618
 
619
                                        o_wb_ack <= 1'b0;
620
                                        o_wb_stall <= 1'b1;
621
                                        end
622
                                2'b11: begin // Read ID register
623
                                        state <= `WBQSPI_READ_ID_CMD;
624
                                        spi_wr <= 1'b1;
625
                                        spi_len <= 2'b00;
626
                                        spi_in <= { 8'h9f, 24'h00};
627
 
628
                                        o_wb_ack <= 1'b0;
629
                                        o_wb_stall <= 1'b1;
630
                                        end
631
                                endcase
632
                        end
633
                end
634
//
635
//
636
//      READ DATA section: for both data and commands
637
//
638
        end else if (state == `WBQSPI_RD_DUMMY)
639
        begin
640
                o_wb_ack   <= 1'b0;
641
                o_wb_stall <= 1'b1;
642
 
643
                spi_wr <= 1'b1; // Non-stop
644
                // Need to read one byte of dummy data,
645
                // just to consume 8 clocks
646
                spi_in <= { 8'h00, 24'h00 };
647
                spi_len <= 2'b00; // Read 8 bits
648
                spi_spd <= 1'b0;
649
                spi_hold <= 1'b0;
650
                spif_req<= (spif_req) && (i_wb_cyc);
651
 
652
                if ((~spi_busy)&&(~o_qspi_cs_n))
653
                        // Our command was accepted
654
                        state <= `WBQSPI_READ_CMD;
655
        end else if (state == `WBQSPI_QRD_ADDRESS)
656
        begin
657
                // We come in here immediately upon issuing a QRD read
658
                // command (8-bits), but we have to pause to give the
659
                // address (24-bits) and mode (8-bits) in quad speed.
660
                o_wb_ack   <= 1'b0;
661
                o_wb_stall <= 1'b1;
662
 
663
                spi_wr <= 1'b1; // Non-stop
664
                spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
665 46 dgisselq
                                spif_addr[(AW-1):0], 2'b00, 8'ha0 };
666 2 dgisselq
                spi_len <= 2'b10; // Write address, not mode byte
667
                spi_spd <= 1'b1;
668
                spi_dir <= 1'b0; // Still writing
669
                spi_hold <= 1'b0;
670
                spif_req<= (spif_req) && (i_wb_cyc);
671
 
672
                if ((~spi_busy)&&(spi_spd))
673
                        // Our command was accepted
674
                        state <= `WBQSPI_QRD_DUMMY;
675
        end else if (state == `WBQSPI_QRD_DUMMY)
676
        begin
677
                o_wb_ack   <= 1'b0;
678
                o_wb_stall <= 1'b1;
679
 
680
                spi_wr <= 1'b1; // Non-stop
681
                spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
682
                spi_len <= 2'b10; // Write 8 bits
683
                spi_spd <= 1'b1;
684
                spi_dir <= 1'b0; // Still writing
685
                spi_hold <= 1'b0;
686
                spif_req<= (spif_req) && (i_wb_cyc);
687
 
688
                if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
689
                        // Our command was accepted
690
                        state <= `WBQSPI_READ_CMD;
691
        end else if (state == `WBQSPI_READ_CMD)
692
        begin // Issue our first command to read 32 bits.
693
                o_wb_ack   <= 1'b0;
694
                o_wb_stall <= 1'b1;
695
 
696
                spi_wr <= 1'b1;
697
                spi_in <= { 8'hff, 24'h00 }; // Empty
698
                spi_len <= 2'b11; // Read 32 bits
699
                spi_dir <= 1'b1; // Now reading
700
                spi_hold <= 1'b0;
701
                spif_req<= (spif_req) && (i_wb_cyc);
702
                if ((spi_valid)&&(spi_len == 2'b11))
703
                        state <= `WBQSPI_READ_DATA;
704
        end else if (state == `WBQSPI_READ_DATA)
705
        begin
706
                // Pipelined read support
707 46 dgisselq
                spi_wr <=((i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
708 2 dgisselq
                spi_in <= 32'h00;
709
                spi_len <= 2'b11;
710
                // Don't adjust the speed here, it was set in the setup
711
                spi_dir <= 1'b1;        // Now we get to read
712
                // Don't let the device go to idle until the bus cycle ends.
713
                //      This actually prevents a *really* nasty race condition,
714
                //      where the strobe comes in after the lower level device
715
                //      has decided to stop waiting.  The write is then issued,
716
                //      but no one is listening.  By leaving the device open,
717
                //      the device is kept in a state where a valid strobe
718
                //      here will be useful.  Of course, we don't accept
719
                //      all commands, just reads.  Further, the strobe needs
720
                //      to be high for two clocks cycles without changing
721
                //      anything on the bus--one for us to notice it and pull
722
                //      our head out of the sand, and a second for whoever
723
                //      owns the bus to realize their command went through.
724
                spi_hold <= 1'b1;
725
                spif_req<= (spif_req) && (i_wb_cyc);
726
                if ((spi_valid)&&(~spi_in[31]))
727
                begin // Single pulse acknowledge and write data out
728
                        o_wb_ack <= spif_req;
729
                        o_wb_stall <= (~spi_wr);
730
                        // adjust endian-ness to match the PC
731 46 dgisselq
                        o_wb_data <= spi_out;
732 2 dgisselq
                        state <= (spi_wr)?`WBQSPI_READ_DATA
733
                                : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
734
                        spif_req <= spi_wr;
735
                        spi_hold <= (~spi_wr);
736
                        if (spi_wr)
737
                                spif_addr <= i_wb_addr;
738
                end else if (~i_wb_cyc)
739
                begin // FAIL SAFE: If the bus cycle ends, forget why we're
740
                        // here, just go back to idle
741
                        state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
742
                        spi_hold <= 1'b0;
743
                        o_wb_ack <= 1'b0;
744
                        o_wb_stall <= 1'b1;
745
                end else begin
746
                        o_wb_ack <= 1'b0;
747
                        o_wb_stall <= 1'b1;
748
                end
749
        end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
750
        begin // Wait 'til idle, but then go to fast read idle instead of full
751
                spi_wr     <= 1'b0;     // idle
752
                spi_hold   <= 1'b0;
753
                o_wb_stall <= 1'b1;
754
                o_wb_ack   <= 1'b0;
755
                spif_req   <= 1'b0;
756
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
757
                begin // clearing of the SPI port before moving on
758
                        state <= `WBQSPI_RDIDLE;
759
                        o_wb_stall <= 1'b0;
760
                        o_wb_ack   <= 1'b0;// Shouldn't be acking anything here
761
                end
762
        end else if (state == `WBQSPI_READ_ID_CMD)
763
        begin // We came into here immediately after issuing a 0x9f command
764
                // Now we need to read 32 bits of data.  Result should be
765
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
766
                // by the number of extended bytes available 8'h4d).
767
                o_wb_ack <= 1'b0;
768
                o_wb_stall<= 1'b1;
769
 
770
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
771
                spi_len <= 2'b11; // 32 bits of data are ... useful
772
                spi_in <= 32'h00; // Irrelevant
773
                spi_spd <= 1'b0; // Slow speed
774
                spi_dir <= 1'b1; // Reading
775
                spi_hold <= 1'b0;
776
                spif_req <= (spif_req) && (i_wb_cyc);
777
                if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
778
                        // Our command was accepted, now go read the result
779
                        state <= `WBQSPI_READ_ID;
780
        end else if (state == `WBQSPI_READ_ID)
781
        begin
782
                o_wb_ack <= 1'b0; // Assuming we're still waiting
783
                o_wb_stall <= 1'b1;
784
 
785
                spi_wr <= 1'b0; // No more writes, we've already written the cmd
786
                spi_hold <= 1'b0;
787
                spif_req <= (spif_req) && (i_wb_cyc);
788
 
789
                // Here, we just wait until the result comes back
790
                // The problem is, the result may be the previous result.
791
                // So we use spi_len as an indicator
792
                spi_len <= 2'b00;
793
                if((spi_valid)&&(spi_len==2'b00))
794
                begin // Put the results out as soon as possible
795
                        o_wb_data <= spi_out[31:0];
796
                        o_wb_ack <= spif_req;
797
                        spif_req <= 1'b0;
798
                end else if ((~spi_busy)&&(o_qspi_cs_n))
799
                begin
800
                        state <= `WBQSPI_IDLE;
801
                        o_wb_stall <= 1'b0;
802
                end
803
        end else if (state == `WBQSPI_READ_STATUS)
804
        begin // We enter after the command has been given, for now just
805
                // read and return
806
                spi_wr <= 1'b0;
807
                o_wb_ack <= 1'b0;
808
                spi_hold <= 1'b0;
809
                spif_req <= (spif_req) && (i_wb_cyc);
810
                if (spi_valid)
811
                begin
812
                        o_wb_ack <= spif_req;
813
                        o_wb_stall <= 1'b1;
814
                        spif_req <= 1'b0;
815
                        last_status <= spi_out[7:0];
816
                        write_in_progress <= spi_out[0];
817
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
818
                        begin // status, 'cause we're writing
819
                                o_wb_data <= { spi_out[0],
820
                                        dirty_sector, spi_busy,
821
                                        ~write_protect,
822
                                        quad_mode_enabled,
823
                                        {(29-ADDRESS_WIDTH){1'b0}},
824
                                        erased_sector, 14'h000 };
825
                        end else begin
826
                                o_wb_data <= { 24'h00, spi_out[7:0] };
827
                        end
828
                end
829
 
830
                if ((~spi_busy)&&(~spi_wr))
831
                        state <= `WBQSPI_IDLE;
832
        end else if (state == `WBQSPI_READ_CONFIG)
833
        begin // We enter after the command has been given, for now just
834
                // read and return
835
                spi_wr <= 1'b0;
836
                o_wb_ack <= 1'b0;
837
                o_wb_stall <= 1'b1;
838
                spi_hold <= 1'b0;
839
                spif_req <= (spif_req) && (i_wb_cyc);
840
 
841
                if (spi_valid)
842
                begin
843
                        o_wb_data <= { 24'h00, spi_out[7:0] };
844
                        quad_mode_enabled <= spi_out[1];
845
                end
846
 
847
                if ((~spi_busy)&&(~spi_wr))
848
                begin
849
                        state <= `WBQSPI_IDLE;
850
                        o_wb_ack   <= spif_req;
851
                        o_wb_stall <= 1'b0;
852
                        spif_req <= 1'b0;
853
                end
854
 
855
//
856
//
857
//      Write/erase data section
858
//
859
`ifndef READ_ONLY
860
        end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
861
        begin
862
                o_wb_stall <= 1'b1;
863
                o_wb_ack   <= 1'b0;
864
                spi_wr <= 1'b0;
865
                spif_req<= (spif_req) && (i_wb_cyc);
866
                if (~spi_busy)
867
                begin
868
                        spi_wr   <= 1'b1;
869
                        spi_in   <= { 8'h05, 24'h0000 };
870
                        spi_hold <= 1'b1;
871
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
872
                        state <= `WBQSPI_CHECK_WIP_CLEAR;
873
                        spi_spd  <= 1'b0; // Slow speed
874
                        spi_dir  <= 1'b0;
875
                end
876
        end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
877
        begin
878
                o_wb_stall <= 1'b1;
879
                o_wb_ack   <= 1'b0;
880
                // Repeat as often as necessary until we are clear
881
                spi_wr <= 1'b1;
882
                spi_in <= 32'h0000; // Values here are actually irrelevant
883
                spi_hold <= 1'b1;
884
                spi_len <= 2'b00; // One byte at a time
885
                spi_spd  <= 1'b0; // Slow speed
886
                spi_dir  <= 1'b0;
887
                spif_req<= (spif_req) && (i_wb_cyc);
888
                if ((spi_valid)&&(~spi_out[0]))
889
                begin
890
                        state <= `WBQSPI_CHECK_WIP_DONE;
891
                        spi_wr   <= 1'b0;
892
                        spi_hold <= 1'b0;
893
                        write_in_progress <= 1'b0;
894
                        last_status <= spi_out[7:0];
895
                end
896
        end else if (state == `WBQSPI_CHECK_WIP_DONE)
897
        begin
898
                o_wb_stall <= 1'b1;
899
                o_wb_ack   <= 1'b0;
900
                // Let's let the SPI port come back to a full idle,
901
                // and the chip select line go low before continuing
902
                spi_wr   <= 1'b0;
903
                spi_len  <= 2'b00;
904
                spi_hold <= 1'b0;
905
                spi_spd  <= 1'b0; // Slow speed
906
                spi_dir  <= 1'b0;
907
                spif_req<= (spif_req) && (i_wb_cyc);
908
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
909
                begin
910
                        spi_wr   <= 1'b0;
911
                        spi_hold <= 1'b0;
912
 
913
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
914
                        4'b00??: begin // Read data from ... somewhere
915
                                spi_wr     <= 1'b1;     // Write cmd to device
916
                                if (quad_mode_enabled)
917
                                begin
918
                                        spi_in <= { 8'heb,
919
                                                {(24-ADDRESS_WIDTH){1'b0}},
920 46 dgisselq
                                                spif_addr[(AW-1):0], 2'b00 };
921 2 dgisselq
                                        state <= `WBQSPI_QRD_ADDRESS;
922
                                        // spi_len    <= 2'b00; // single byte, cmd only
923
                                end else begin
924
                                        spi_in <= { 8'h0b,
925
                                                {(24-ADDRESS_WIDTH){1'b0}},
926 46 dgisselq
                                                spif_addr[(AW-1):0], 2'b00 };
927 2 dgisselq
                                        state <= `WBQSPI_RD_DUMMY;
928
                                        spi_len    <= 2'b11; // Send cmd and addr
929
                                end end
930
                        4'b10??: begin // Write data to ... anywhere
931
                                spi_wr <= 1'b1;
932
                                spi_len <= 2'b00; // 8 bits
933
                                // Send a write enable command
934
                                spi_in <= { 8'h06, 24'h00 };
935
                                state <= `WBQSPI_WEN;
936
                                end
937
                        4'b0110: begin // Read status register
938
                                state <= `WBQSPI_READ_STATUS;
939
                                spi_wr <= 1'b1;
940
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
941
                                spi_in <= { 8'h05, 24'h00};
942
                                end
943
                        4'b0111: begin
944
                                state <= `WBQSPI_READ_ID_CMD;
945
                                spi_wr <= 1'b1;
946
                                spi_len <= 2'b00;
947
                                spi_in <= { 8'h9f, 24'h00};
948
                                end
949
                        default: begin //
950
                                o_wb_stall <= 1'b1;
951
                                o_wb_ack <= spif_req;
952
                                state <= `WBQSPI_WAIT_TIL_IDLE;
953
                                end
954
                        endcase
955
                // spif_cmd   <= i_wb_we;
956
                // spif_addr  <= i_wb_addr;
957
                // spif_data  <= i_wb_data;
958
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
959
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
960
                end
961
        end else if (state == `WBQSPI_WEN)
962
        begin // We came here after issuing a write enable command
963
                spi_wr <= 1'b0;
964
                o_wb_ack <= 1'b0;
965
                o_wb_stall <= 1'b1;
966
                spif_req<= (spif_req) && (i_wb_cyc);
967
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
968
                        state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
969
                        // state <= `WBQSPI_PP;
970
        end else if (state == `WBQSPI_PP)
971
        begin // We come here under a full stop / full port idle mode
972
                // Issue our command immediately
973
                spi_wr <= 1'b1;
974
                spi_in <= { 8'h02,
975
                                {(24-ADDRESS_WIDTH){1'b0}},
976 46 dgisselq
                                spif_addr[(AW-1):0], 2'b00 };
977 2 dgisselq
                spi_len <= 2'b11;
978
                spi_hold <= 1'b1;
979
                spi_spd  <= 1'b0;
980
                spi_dir  <= 1'b0; // Writing
981
                spif_req<= (spif_req) && (i_wb_cyc);
982
 
983
                // Once we get busy, move on
984
                if (spi_busy)
985
                        state <= `WBQSPI_WR_DATA;
986
                if (spif_sector == erased_sector)
987
                        dirty_sector <= 1'b1;
988
        end else if (state == `WBQSPI_QPP)
989
        begin // We come here under a full stop / full port idle mode
990
                // Issue our command immediately
991
                spi_wr <= 1'b1;
992
                spi_in <= { 8'h32,
993
                                {(24-ADDRESS_WIDTH){1'b0}},
994 46 dgisselq
                                spif_addr[(AW-1):0], 2'b00 };
995 2 dgisselq
                spi_len <= 2'b11;
996
                spi_hold <= 1'b1;
997
                spi_spd  <= 1'b0;
998
                spi_dir  <= 1'b0; // Writing
999
                spif_req<= (spif_req) && (i_wb_cyc);
1000
 
1001
                // Once we get busy, move on
1002
                if (spi_busy)
1003
                begin
1004
                        // spi_wr is irrelevant here ...
1005
                        // Set the speed value once, but wait til we get busy
1006
                        // to do so.
1007
                        spi_spd <= 1'b1;
1008
                        state <= `WBQSPI_WR_DATA;
1009
                end
1010
                if (spif_sector == erased_sector)
1011
                        dirty_sector <= 1'b1;
1012
        end else if (state == `WBQSPI_WR_DATA)
1013
        begin
1014
                o_wb_stall <= 1'b1;
1015
                o_wb_ack   <= 1'b0;
1016
                spi_wr   <= 1'b1; // write without waiting
1017 46 dgisselq
                spi_in   <= spif_data;
1018 2 dgisselq
                spi_len  <= 2'b11; // Write 4 bytes
1019
                spi_hold <= 1'b1;
1020
                if (~spi_busy)
1021
                begin
1022
                        o_wb_ack <= spif_req; // Ack when command given
1023
                        state <= `WBQSPI_WR_BUS_CYCLE;
1024
                end
1025
                spif_req<= (spif_req) && (i_wb_cyc);
1026
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
1027
        begin
1028
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
1029
                o_wb_stall <= 1'b1;
1030
                spi_wr <= 1'b0;
1031
                spi_hold <= 1'b1;
1032
                write_in_progress <= 1'b1;
1033
                spif_req<= (spif_req) && (i_wb_cyc);
1034
                if (~i_wb_cyc)
1035
                begin
1036
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1037
                        spi_hold <= 1'b0;
1038
                end else if (spi_wr)
1039
                begin // Give the SPI a chance to get busy on the last write
1040
                        // Do nothing here.
1041
                end else if ((i_wb_data_stb)&&(i_wb_we)
1042
                                &&(i_wb_addr == (spif_addr+1))
1043 46 dgisselq
                                &&(i_wb_addr[(AW-1):6]==spif_addr[(AW-1):6]))
1044 2 dgisselq
                begin
1045
                        spif_cmd  <= 1'b1;
1046
                        spif_data <= i_wb_data;
1047
                        spif_addr <= i_wb_addr;
1048
                        spif_ctrl  <= 1'b0;
1049
                        spif_req<= 1'b1;
1050
                        // We'll keep the bus stalled on this request
1051
                        // for a while
1052
                        state <= `WBQSPI_WR_DATA;
1053
                        o_wb_ack   <= 1'b0;
1054
                        o_wb_stall <= 1'b0;
1055
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
1056
                begin
1057
                        spi_hold <= 1'b0;
1058
                        spi_wr   <= 1'b0;
1059
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1060
                end // Otherwise we stay here
1061
        end else if (state == `WBQSPI_WRITE_CONFIG)
1062
        begin // We enter immediately after commanding a WEN
1063
                o_wb_ack   <= 1'b0;
1064
                o_wb_stall <= 1'b1;
1065
 
1066
                spi_len <= 2'b10;
1067
                spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
1068
                spi_wr <= 1'b0;
1069
                spi_hold <= 1'b0;
1070
                spif_req <= (spif_req) && (i_wb_cyc);
1071
                if ((~spi_busy)&&(~spi_wr))
1072
                begin
1073
                        spi_wr <= 1'b1;
1074
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1075
                        write_in_progress <= 1'b1;
1076
                        quad_mode_enabled <= spif_data[1];
1077
                end
1078
        end else if (state == `WBQSPI_WRITE_STATUS)
1079
        begin // We enter immediately after commanding a WEN
1080
                o_wb_ack   <= 1'b0;
1081
                o_wb_stall <= 1'b1;
1082
 
1083
                spi_len <= 2'b01;
1084
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
1085
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
1086
                spi_wr <= 1'b0;
1087
                spi_hold <= 1'b0;
1088
                spif_req <= (spif_req) && (i_wb_cyc);
1089
                if ((~spi_busy)&&(~spi_wr))
1090
                begin
1091
                        spi_wr <= 1'b1;
1092
                        last_status <= spif_data[7:0];
1093
                        write_in_progress <= 1'b1;
1094
                        if(((last_status[6])||(last_status[5]))
1095
                                &&((~spif_data[6])&&(~spif_data[5])))
1096
                                state <= `WBQSPI_CLEAR_STATUS;
1097
                        else
1098
                                state <= `WBQSPI_WAIT_TIL_IDLE;
1099
                end
1100
        end else if (state == `WBQSPI_ERASE_CMD)
1101
        begin // Know that WIP is clear on entry, WEN has just been commanded
1102
                spi_wr     <= 1'b0;
1103
                o_wb_ack   <= 1'b0;
1104
                o_wb_stall <= 1'b1;
1105
                spi_hold   <= 1'b0;
1106
                spi_spd <= 1'b0;
1107
                spi_dir <= 1'b0;
1108
                spif_req <= (spif_req) && (i_wb_cyc);
1109
 
1110
                // Here's the erase command
1111
                spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
1112
                spi_len <= 2'b11; // 32 bit write
1113
                // together with setting our copy of the WIP bit
1114
                write_in_progress <= 1'b1;
1115
                // keeping track of which sector we just erased
1116 46 dgisselq
                erased_sector <= spif_data[(AW-1):14];
1117 2 dgisselq
                // and marking this erase sector as no longer dirty
1118
                dirty_sector <= 1'b0;
1119
 
1120
                // Wait for a full stop before issuing this command
1121
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
1122
                begin // When our command is accepted, move to the next state
1123
                        spi_wr <= 1'b1;
1124
                        state <= `WBQSPI_ERASE_BLOCK;
1125
                end
1126
        end else if (state == `WBQSPI_ERASE_BLOCK)
1127
        begin
1128
                spi_wr     <= 1'b0;
1129
                spi_hold   <= 1'b0;
1130
                o_wb_stall <= 1'b1;
1131
                o_wb_ack   <= 1'b0;
1132
                spif_req <= (spif_req) && (i_wb_cyc);
1133
                // When the port clears, we can head back to idle
1134 46 dgisselq
                //      No ack necessary, we ackd before getting
1135
                //      here.
1136 2 dgisselq
                if ((~spi_busy)&&(~spi_wr))
1137
                        state <= `WBQSPI_IDLE;
1138
        end else if (state == `WBQSPI_CLEAR_STATUS)
1139
        begin // Issue a clear status command
1140
                spi_wr <= 1'b1;
1141
                spi_hold <= 1'b0;
1142
                spi_len <= 2'b00; // 8 bit command
1143
                spi_in <= { 8'h30, 24'h00 };
1144
                spi_spd <= 1'b0;
1145
                spi_dir <= 1'b0;
1146
                last_status[6:5] <= 2'b00;
1147
                spif_req <= (spif_req) && (i_wb_cyc);
1148
                if ((spi_wr)&&(~spi_busy))
1149
                        state <= `WBQSPI_WAIT_TIL_IDLE;
1150
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
1151
        begin // We are now in read status register mode
1152
 
1153
                // No bus commands have (yet) been given
1154
                o_wb_stall <= 1'b1;
1155
                o_wb_ack   <= 1'b0;
1156
                spif_req <= (spif_req) && (i_wb_cyc);
1157
 
1158
                // Stay in this mode unless/until we get a command, or
1159
                //      the write is over
1160
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
1161
                                &&(write_in_progress));
1162
                spi_len <= 2'b00; // 8 bit reads
1163
                spi_spd <= 1'b0;  // SPI, not quad
1164
                spi_dir <= 1'b1;  // Read
1165
                if (spi_valid)
1166
                begin
1167
                        write_in_progress <= spi_out[0];
1168
                        if ((~spi_out[0])&&(write_in_progress))
1169
                                o_interrupt <= 1'b1;
1170
                end else
1171
                        o_interrupt <= 1'b0;
1172
 
1173
                if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
1174
                begin // We can now go to idle and process a command
1175
                        o_wb_stall <= 1'b0;
1176
                        o_wb_ack   <= 1'b0;
1177
                        state <= `WBQSPI_IDLE;
1178
                end
1179
`endif //       !READ_ONLY
1180
        end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
1181
        begin
1182
                spi_wr     <= 1'b0;
1183
                spi_hold   <= 1'b0;
1184
                o_wb_stall <= 1'b1;
1185
                o_wb_ack   <= 1'b0;
1186
                spif_req   <= 1'b0;
1187
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
1188
                begin // clearing of the SPI port before moving on
1189
                        state <= `WBQSPI_IDLE;
1190
                        o_wb_stall <= 1'b0;
1191
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
1192
                end
1193
        end
1194
        end
1195
 
1196
        // Command and control during the reset sequence
1197 11 dgisselq
        assign  o_qspi_cs_n = (spif_override)?alt_cmd :w_qspi_cs_n;
1198
        assign  o_qspi_sck  = (spif_override)?alt_ctrl:w_qspi_sck;
1199
        assign  o_qspi_mod  = (spif_override)?  2'b01 :w_qspi_mod;
1200
        assign  o_qspi_dat  = (spif_override)?  4'b00 :w_qspi_dat;
1201 2 dgisselq
endmodule

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