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[/] [s6soc/] [trunk/] [sw/] [dev/] [resetdump.s] - Blame information for rev 53

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
;;
;; Filename:    resetdump.s
;;
;; Project:     CMod S6 System on a Chip, ZipCPU demonstration project
;;
;; Purpose:     While most of my ZipCPU programs to date have started with a
;;              simple assembly script to load the stack and call the program
;;      entry point, this is different.  This is a very complicated startup
;;      script designed to dump all of the internal information to the CPU
;;      to a UART output port.  This is on purpose.  Indeed, this may be my
;;      only means of debugging the device once it goes bad:
;;
;;      - To set a breakpoint
;;              at the location desired call kpanic(), the CPU will dump its
;;                      variables and wait for a button press to restart.
;;              sometime before the desired clock, set the watchdog timer.
;;                      When the watchdog expires, the CPU will restart. 
;;                      Adjusting the watchdog will adjust how long the CPU
;;                      waits before restarting, and may also adjust what
;;                      instructions you find going on
;;
;;      - In hardware, you can also set the scope.  On boot up, this resetdump
;;              startup will dump the value of the scope to the UART.
;;
;;      Of course, this all depends upon someone listening on the uart.  That's
;;      the purpose of the dumpuart.cpp program in the sw/host directory.
;;      That file will capture the dump so it can be examined later.
;;
;; Creator:     Dan Gisselquist, Ph.D.
;;              Gisselquist Technology, LLC
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
;;
;; Copyright (C) 2015-2017, Gisselquist Technology, LLC
;;
;; This program is free software (firmware): you can redistribute it and/or
;; modify it under the terms of  the GNU General Public License as published
;; by the Free Software Foundation, either version 3 of the License, or (at
;; your option) any later version.
;;
;; This program is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
;; for more details.
;;
;; You should have received a copy of the GNU General Public License along
;; with this program.  (It's in the $(ROOT)/doc directory, run make with no
;; target there if the PDF file isn't present.)  If not, see
;; <http://www.gnu.org/licenses/> for a copy.
;;
;; License:     GPL, v3, as defined and found on www.gnu.org,
;;              http://www.gnu.org/licenses/gpl.html
;;
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//
;;
;;
        .section        .start
        .global         _start
        .type           _start,@function
_start:
; Upon reset, we must output our registers to the UART, lest we reset because
; of a crash
        SW      R0,(DBG)
        LDI     0x00000002,R0
        SW      R0,(SCOPE)
        JSR     internal_kpanic
        LDI     _top_of_stack,SP
        LDI     gostr,R1
        JSR     raw_put_string
        LDI     0x7fffffff,R1
        SW      R1,(PIC)
;       ; Turn on the button interrupt--so we can stop on interrupt
;       LDI     0x80010001,R1
;       SW      R1,(PIC)
        ;LDI    0xff000002,R1
        ;SW     R1,(SCOPE)
; For running in supervisor mode:
;       JSR     entry
; otherwise ..
        MOV     entry(PC),uPC
        MOV     SP,uSP
        RTU
        JMP     kpanic
 
        .global         kpanic
        .type           kpanic,@function
kpanic:
        SW      R0,(DBG)
        SW      R1,4(DBG)
        SW      R2,8(DBG)
        LDI     panicstr, R1
        JSR     raw_put_string
        LW      4(DBG),R1
        LW      8(DBG),R2
        JSR     internal_kpanic
kpanic_wait_for_button_release:
        LW      (SPIO),R0
        TEST    0x010,R0
        BNZ     kpanic_wait_for_button_release
kpanic_wait_for_button:
        LW      (SPIO),R0
        TEST    0x010,R0
        BZ      kpanic_wait_for_button
        BRA     _start
        HALT
 
internal_kpanic:
        ; The original R0 is stored in (DBG)
        SW      R1,4(DBG)
        SW      R2,8(DBG)
        SW      R0,12(DBG)      ; Our return address
 
        ; Make sure the watchdog is off
        LDI     0,R1
        SW      R1,0x40c
 
        ; R0
        LDI     0,R1
        LW      (DBG),R2
        JSR     uart_put_reg_value
 
        ; R1
        LDI     1,R1
        LW      4(DBG),R2
        JSR     uart_put_reg_value
        ; R2
        LDI     2,R1
        LW      8(DBG),R2
        JSR     uart_put_reg_value
        ; R3
        LDI     3,R1
        MOV     R3,R2
        JSR     uart_put_reg_value
 
        ; R4
        LDI     4,R1
        MOV     R4,R2
        JSR     uart_put_reg_value
 
        ; R5
        LDI     5,R1
        MOV     R5,R2
        JSR     uart_put_reg_value
 
        ; R6
        LDI     6,R1
        MOV     R6,R2
        JSR     uart_put_reg_value
 
        ; R7
        LDI     7,R1
        MOV     R7,R2
        JSR     uart_put_reg_value
 
        ; R8
        LDI     8,R1
        MOV     R8,R2
        JSR     uart_put_reg_value
 
        ; R9
        LDI     9,R1
        MOV     R9,R2
        JSR     uart_put_reg_value
 
        ; R10
        LDI     10,R1
        MOV     R10,R2
        JSR     uart_put_reg_value
 
        ; R11
        LDI     11,R1
        MOV     R11,R2
        JSR     uart_put_reg_value
 
        ; R12
        LDI     12,R1
        MOV     R12,R2
        JSR     uart_put_reg_value
 
        ; SP
        LDI     13,R1
        MOV     R13,R2
        JSR     uart_put_reg_value
 
        ; uR0
        LDI     16,R1
        MOV     uR0,R2
        JSR     uart_put_reg_value
 
        ; uR1
        LDI     17,R1
        MOV     uR1,R2
        JSR     uart_put_reg_value
 
        LDI     18,R1
        MOV     uR2,R2
        JSR     uart_put_reg_value
 
        LDI     19,R1
        MOV     uR3,R2
        JSR     uart_put_reg_value
 
        LDI     20,R1
        MOV     uR4,R2
        JSR     uart_put_reg_value
 
        LDI     21,R1
        MOV     uR5,R2
        JSR     uart_put_reg_value
 
        LDI     22,R1
        MOV     uR6,R2
        JSR     uart_put_reg_value
 
        LDI     23,R1
        MOV     uR7,R2
        JSR     uart_put_reg_value
 
        LDI     24,R1
        MOV     uR8,R2
        JSR     uart_put_reg_value
 
        LDI     25,R1
        MOV     uR9,R2
        JSR     uart_put_reg_value
 
        LDI     26,R1
        MOV     uR10,R2
        JSR     uart_put_reg_value
 
        LDI     27,R1
        MOV     uR11,R2
        JSR     uart_put_reg_value
 
        LDI     28,R1
        MOV     uR12,R2
        JSR     uart_put_reg_value
 
        ; uSP
        LDI     29,R1
        MOV     uSP,R2
        JSR     uart_put_reg_value
 
        ; uCC
        LDI     30,R1
        MOV     uCC,R2
        JSR     uart_put_reg_value
 
        ; uPC
        LDI     31,R1
        MOV     uPC,R2
        JSR     uart_put_reg_value
 
;stack_mem_dump:
;       LDI     0,R4
;       LDI     _top_of_stack,R5
;stack_mem_dump_loop:
;       MOV     R4,R1
;       LW      (R5),R2
;       JSR     uart_put_stack_value
;       ADD     4,R4
;       SUB     4,R5
;       CMP     256,R4
;       BLT     stack_mem_dump_loop
 
; Get prepared for a proper start by setting our stack register
        LDI     _top_of_stack,SP
 
        BRA     dump_scope
        ; BRA   end_internal_panic
 
; Now, do a full dump of all memory--all registers are available to us
dump_memory:
        LDI     RAM,R5
        LDI     0x0fff,R6
        LDI     0x0f8,R7
        SW      R7,(SPIO)
full_mem_dump_loop:
        MOV     R5,R1
        LW      (R5),R2
        JSR     uart_dump_mem_value
        LDI     0x0f2,R7
        SW      R7,(SPIO)
 
        ADD     4,R5
        SUB     1,R6
        BGE     full_mem_dump_loop
 
        LDI     0x0f5,R7
        SW      R7,(SPIO)
 
dump_scope:
; Finally, do a full dump of the scope--if it had triggered
;   First, dump the scope control word
        LDI     SCOPE,R7        ; R7 = Debugging scope address
        MOV     R7,R1
        LW      (R7),R2
        MOV     R2,R5           ; R5 will not be changed by a subroutine
        JSR     uart_dump_mem_value
;   Then test whether or not the scope has stopped
        LDI     0x40000000,R1
        TEST    R1,R5
;   If not, start our kernel.
        BZ      dump_buserr
;   Otherwise, calculate the size of the scope
        LSR     20,R5
        AND     0x1f,R5
        LDI     1,R6
        LSL     R5,R6   ; R6 is now the size (number of words) of the scope
        SUB     1,R6    ; Now it is one less than the size,2 support the BGE l8r
;   And start dumping
        ADD     4,R7    ; Get the scope data address
dump_scope_loop:
        MOV     R7,R1
        LW      (R7),R2
        JSR     uart_dump_mem_value
        SUB     1,R6
        BGE     dump_scope_loop
 
dump_buserr:
; Dump a bus error address, if used
        LDI     buserr_header, R1
        JSR     raw_put_string
        LDI     BUSERR,R1
        LW      (R1),R2
        JSR     uart_dump_mem_value
 
end_internal_panic:
        LDI     doublenewline,R1
        JSR     raw_put_string
        LDI     0x0ff,R7
        SW      R7,(SPIO)
        LW      12(DBG),PC
        RTN
 
; R0 is return address
; R1 is register ID
; R2 is register value to output
uart_put_reg_value:
        SW      R0,16(DBG)
        SW      R2,20(DBG)
        SW      R3,24(DBG)
        MOV     R1,R2
        LDI     'u',R1
        CMP     16,R2
        LDILO.LT 's',R1
        SUB.GE  16,R2
        JSR     raw_put_uart
        LDI     '0',R1
        CMP     10,R2
        LDILO.GE '1',R1
        SUB.GE  10,R2
        JSR     raw_put_uart
        MOV     R2,R1
        AND     15,R1
        JSR     get_hex
        JSR     raw_put_uart
        LDI     ':',R1
        JSR     raw_put_uart
        LW      20(DBG),R2
        LDI     8,R3
uart_put_loop:
        MOV     R2,R1
        LSR     28,R1
        LSL     4,R2
        JSR     get_hex
        JSR     raw_put_uart
        SUB     1,R3
        BNZ     uart_put_loop
        LDI     newline, R1
        JSR     raw_put_string
        LW      16(DBG),R0
        LW      20(DBG),R2
        LW      24(DBG),R3
        RTN
 
uart_dump_mem_value:
;       R0 = return address
;       R1 = Memory address
;       R2 = Memory Value
; Local: R3 = working value
        SW      R0,28(DBG)
        MOV     R1,R3           ; R3 = Memory address
        MOV     R2,R4           ; R4 = Memory Value
        LDI     memopenstr,R1
        JSR     raw_put_string
        ; Set up a loop to dump things
        LSL     16,R3           ; Ignore the first 16 bits
        LDI     4,R2            ; We're going to do four hex digits here
        ;
uart_put_mem_address_loop:
        MOV     R3,R1
        LSR     28,R1
        LSL     4,R3
        JSR     get_hex
        JSR     raw_put_uart
        SUB     1,R2
        BNZ     uart_put_mem_address_loop
        ; Put some transition characters
        LDI     memmidstr,R1
        JSR     raw_put_string
 
        ; Set up a loop to dump the memory value now
        LDI     8,R2
uart_put_mem_value_loop:
        MOV     R4,R1
        LSR     28,R1
        LSL     4,R4
        JSR     get_hex
        JSR     raw_put_uart
        SUB     1,R2
        BNZ     uart_put_mem_value_loop
        ; Clear the line
        LDI     newline,R1
        JSR     raw_put_string
        ; And return from our subroutine
        LW      28(DBG),R0
        RTN
 
get_hex:
        ADD     0x30,R1
        CMP     0x3a,R1
        ADD.GE  7,R1    ; Add 'A'-'0'-10
        JMP     R0
 
; R0 is the return address
; R1 is the string address
raw_put_string:
        SW      R0,36(DBG)
        SW      R2,40(DBG)
        MOV     R1,R2
raw_put_string_next:
        LB      (R2),R1
        CMP     0,R1
        LW.Z    36(DBG),R0
        LW.Z    40(DBG),R2
        RTN.Z
        ADD     1,R2
        MOV     raw_put_string_next(PC),R0
        BRA     raw_put_uart
 
; R0 is return address,
; R1 is value to transmit
raw_put_uart:
        SW      R2,32(DBG)
        LDI     INT_UARTTX,R2
        SW      R2,(PIC)        ; Clear the PIC, turn off interrupts, etc.
raw_put_uart_retest:
        LW      (PIC),R2
        TEST    INT_UARTTX,R2
        BZ      raw_put_uart_retest
        SW      R1,(UART)
        LW      32(DBG),R2
        JMP     R0
 
        .section        .fixdata
DBG:
.int    0,0,0,0,0,0,0,0,0,0
 
.set    INT_UARTRX, 0x040
.set    INT_UARTTX, 0x080
.set    PIC,     0x0400
.set    BUSERR,  0x0404
.set    TMRA,    0x0408
.set    TMRB,    0x040c
.set    PWM,     0x0410
.set    SPIO,    0x0414
.set    GPIO,    0x0418
.set    UART,    0x041c
.set    VERSION, 0x0420
.set    SCOPE,   0x0800
.set    SCOPED,  0x0804
.set    RAM,     0x8000
        .section        .rodata
doublenewline:
        .ascii  "\r\n"
newline:
        .asciz  "\r\n"
buserr_header:
        .string "BusErr: "
panicstr:
        .string "Panic: \r\n"
memopenstr:
        .string "M[0x"
memmidstr:
        .string "]: "
gostr:
        .string "Go!\r\n"
 

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[/] [s6soc/] [trunk/] [sw/] [dev/] [resetdump.s] - Blame information for rev 53

Line No.	Rev	Author	Line
1	53	dgisselq	`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//`
2			`;;`
3			`;; Filename: resetdump.s`
4			`;;`
5			`;; Project: CMod S6 System on a Chip, ZipCPU demonstration project`
6			`;;`
7			`;; Purpose: While most of my ZipCPU programs to date have started with a`
8			`;; simple assembly script to load the stack and call the program`
9			`;; entry point, this is different. This is a very complicated startup`
10			`;; script designed to dump all of the internal information to the CPU`
11			`;; to a UART output port. This is on purpose. Indeed, this may be my`
12			`;; only means of debugging the device once it goes bad:`
13			`;;`
14			`;; - To set a breakpoint`
15			`;; at the location desired call kpanic(), the CPU will dump its`
16			`;; variables and wait for a button press to restart.`
17			`;; sometime before the desired clock, set the watchdog timer.`
18			`;; When the watchdog expires, the CPU will restart.`
19			`;; Adjusting the watchdog will adjust how long the CPU`
20			`;; waits before restarting, and may also adjust what`
21			`;; instructions you find going on`
22			`;;`
23			`;; - In hardware, you can also set the scope. On boot up, this resetdump`
24			`;; startup will dump the value of the scope to the UART.`
25			`;;`
26			`;; Of course, this all depends upon someone listening on the uart. That's`
27			`;; the purpose of the dumpuart.cpp program in the sw/host directory.`
28			`;; That file will capture the dump so it can be examined later.`
29			`;;`
30			`;; Creator: Dan Gisselquist, Ph.D.`
31			`;; Gisselquist Technology, LLC`
32			`;;`
33			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//`
34			`;;`
35			`;; Copyright (C) 2015-2017, Gisselquist Technology, LLC`
36			`;;`
37			`;; This program is free software (firmware): you can redistribute it and/or`
38			`;; modify it under the terms of the GNU General Public License as published`
39			`;; by the Free Software Foundation, either version 3 of the License, or (at`
40			`;; your option) any later version.`
41			`;;`
42			`;; This program is distributed in the hope that it will be useful, but WITHOUT`
43			`;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
44			`;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
45			`;; for more details.`
46			`;;`
47			`;; You should have received a copy of the GNU General Public License along`
48			`;; with this program. (It's in the $(ROOT)/doc directory, run make with no`
49			`;; target there if the PDF file isn't present.) If not, see`
50			`;; <http://www.gnu.org/licenses/> for a copy.`
51			`;;`
52			`;; License: GPL, v3, as defined and found on www.gnu.org,`
53			`;; http://www.gnu.org/licenses/gpl.html`
54			`;;`
55			`;;`
56			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;//`
57			`;;`
58			`;;`
59			`.section .start`
60			`.global _start`
61			`.type _start,@function`
62			`_start:`
63			`; Upon reset, we must output our registers to the UART, lest we reset because`
64			`; of a crash`
65			`SW R0,(DBG)`
66			`LDI 0x00000002,R0`
67			`SW R0,(SCOPE)`
68			`JSR internal_kpanic`
69			`LDI _top_of_stack,SP`
70			`LDI gostr,R1`
71			`JSR raw_put_string`
72			`LDI 0x7fffffff,R1`
73			`SW R1,(PIC)`
74			`; ; Turn on the button interrupt--so we can stop on interrupt`
75			`; LDI 0x80010001,R1`
76			`; SW R1,(PIC)`
77			`;LDI 0xff000002,R1`
78			`;SW R1,(SCOPE)`
79			`; For running in supervisor mode:`
80			`; JSR entry`
81			`; otherwise ..`
82			`MOV entry(PC),uPC`
83			`MOV SP,uSP`
84			`RTU`
85			`JMP kpanic`
86
87			`.global kpanic`
88			`.type kpanic,@function`
89			`kpanic:`
90			`SW R0,(DBG)`
91			`SW R1,4(DBG)`
92			`SW R2,8(DBG)`
93			`LDI panicstr, R1`
94			`JSR raw_put_string`
95			`LW 4(DBG),R1`
96			`LW 8(DBG),R2`
97			`JSR internal_kpanic`
98			`kpanic_wait_for_button_release:`
99			`LW (SPIO),R0`
100			`TEST 0x010,R0`
101			`BNZ kpanic_wait_for_button_release`
102			`kpanic_wait_for_button:`
103			`LW (SPIO),R0`
104			`TEST 0x010,R0`
105			`BZ kpanic_wait_for_button`
106			`BRA _start`
107			`HALT`
108
109			`internal_kpanic:`
110			`; The original R0 is stored in (DBG)`
111			`SW R1,4(DBG)`
112			`SW R2,8(DBG)`
113			`SW R0,12(DBG) ; Our return address`
114
115			`; Make sure the watchdog is off`
116			`LDI 0,R1`
117			`SW R1,0x40c`
118
119			`; R0`
120			`LDI 0,R1`
121			`LW (DBG),R2`
122			`JSR uart_put_reg_value`
123
124			`; R1`
125			`LDI 1,R1`
126			`LW 4(DBG),R2`
127			`JSR uart_put_reg_value`
128			`; R2`
129			`LDI 2,R1`
130			`LW 8(DBG),R2`
131			`JSR uart_put_reg_value`
132			`; R3`
133			`LDI 3,R1`
134			`MOV R3,R2`
135			`JSR uart_put_reg_value`
136
137			`; R4`
138			`LDI 4,R1`
139			`MOV R4,R2`
140			`JSR uart_put_reg_value`
141
142			`; R5`
143			`LDI 5,R1`
144			`MOV R5,R2`
145			`JSR uart_put_reg_value`
146
147			`; R6`
148			`LDI 6,R1`
149			`MOV R6,R2`
150			`JSR uart_put_reg_value`
151
152			`; R7`
153			`LDI 7,R1`
154			`MOV R7,R2`
155			`JSR uart_put_reg_value`
156
157			`; R8`
158			`LDI 8,R1`
159			`MOV R8,R2`
160			`JSR uart_put_reg_value`
161
162			`; R9`
163			`LDI 9,R1`
164			`MOV R9,R2`
165			`JSR uart_put_reg_value`
166
167			`; R10`
168			`LDI 10,R1`
169			`MOV R10,R2`
170			`JSR uart_put_reg_value`
171
172			`; R11`
173			`LDI 11,R1`
174			`MOV R11,R2`
175			`JSR uart_put_reg_value`
176
177			`; R12`
178			`LDI 12,R1`
179			`MOV R12,R2`
180			`JSR uart_put_reg_value`
181
182			`; SP`
183			`LDI 13,R1`
184			`MOV R13,R2`
185			`JSR uart_put_reg_value`
186
187			`; uR0`
188			`LDI 16,R1`
189			`MOV uR0,R2`
190			`JSR uart_put_reg_value`
191
192			`; uR1`
193			`LDI 17,R1`
194			`MOV uR1,R2`
195			`JSR uart_put_reg_value`
196
197			`LDI 18,R1`
198			`MOV uR2,R2`
199			`JSR uart_put_reg_value`
200
201			`LDI 19,R1`
202			`MOV uR3,R2`
203			`JSR uart_put_reg_value`
204
205			`LDI 20,R1`
206			`MOV uR4,R2`
207			`JSR uart_put_reg_value`
208
209			`LDI 21,R1`
210			`MOV uR5,R2`
211			`JSR uart_put_reg_value`
212
213			`LDI 22,R1`
214			`MOV uR6,R2`
215			`JSR uart_put_reg_value`
216
217			`LDI 23,R1`
218			`MOV uR7,R2`
219			`JSR uart_put_reg_value`
220
221			`LDI 24,R1`
222			`MOV uR8,R2`
223			`JSR uart_put_reg_value`
224
225			`LDI 25,R1`
226			`MOV uR9,R2`
227			`JSR uart_put_reg_value`
228
229			`LDI 26,R1`
230			`MOV uR10,R2`
231			`JSR uart_put_reg_value`
232
233			`LDI 27,R1`
234			`MOV uR11,R2`
235			`JSR uart_put_reg_value`
236
237			`LDI 28,R1`
238			`MOV uR12,R2`
239			`JSR uart_put_reg_value`
240
241			`; uSP`
242			`LDI 29,R1`
243			`MOV uSP,R2`
244			`JSR uart_put_reg_value`
245
246			`; uCC`
247			`LDI 30,R1`
248			`MOV uCC,R2`
249			`JSR uart_put_reg_value`
250
251			`; uPC`
252			`LDI 31,R1`
253			`MOV uPC,R2`
254			`JSR uart_put_reg_value`
255
256			`;stack_mem_dump:`
257			`; LDI 0,R4`
258			`; LDI _top_of_stack,R5`
259			`;stack_mem_dump_loop:`
260			`; MOV R4,R1`
261			`; LW (R5),R2`
262			`; JSR uart_put_stack_value`
263			`; ADD 4,R4`
264			`; SUB 4,R5`
265			`; CMP 256,R4`
266			`; BLT stack_mem_dump_loop`
267
268			`; Get prepared for a proper start by setting our stack register`
269			`LDI _top_of_stack,SP`
270
271			`BRA dump_scope`
272			`; BRA end_internal_panic`
273
274			`; Now, do a full dump of all memory--all registers are available to us`
275			`dump_memory:`
276			`LDI RAM,R5`
277			`LDI 0x0fff,R6`
278			`LDI 0x0f8,R7`
279			`SW R7,(SPIO)`
280			`full_mem_dump_loop:`
281			`MOV R5,R1`
282			`LW (R5),R2`
283			`JSR uart_dump_mem_value`
284			`LDI 0x0f2,R7`
285			`SW R7,(SPIO)`
286
287			`ADD 4,R5`
288			`SUB 1,R6`
289			`BGE full_mem_dump_loop`
290
291			`LDI 0x0f5,R7`
292			`SW R7,(SPIO)`
293
294			`dump_scope:`
295			`; Finally, do a full dump of the scope--if it had triggered`
296			`; First, dump the scope control word`
297			`LDI SCOPE,R7 ; R7 = Debugging scope address`
298			`MOV R7,R1`
299			`LW (R7),R2`
300			`MOV R2,R5 ; R5 will not be changed by a subroutine`
301			`JSR uart_dump_mem_value`
302			`; Then test whether or not the scope has stopped`
303			`LDI 0x40000000,R1`
304			`TEST R1,R5`
305			`; If not, start our kernel.`
306			`BZ dump_buserr`
307			`; Otherwise, calculate the size of the scope`
308			`LSR 20,R5`
309			`AND 0x1f,R5`
310			`LDI 1,R6`
311			`LSL R5,R6 ; R6 is now the size (number of words) of the scope`
312			`SUB 1,R6 ; Now it is one less than the size,2 support the BGE l8r`
313			`; And start dumping`
314			`ADD 4,R7 ; Get the scope data address`
315			`dump_scope_loop:`
316			`MOV R7,R1`
317			`LW (R7),R2`
318			`JSR uart_dump_mem_value`
319			`SUB 1,R6`
320			`BGE dump_scope_loop`
321
322			`dump_buserr:`
323			`; Dump a bus error address, if used`
324			`LDI buserr_header, R1`
325			`JSR raw_put_string`
326			`LDI BUSERR,R1`
327			`LW (R1),R2`
328			`JSR uart_dump_mem_value`
329
330			`end_internal_panic:`
331			`LDI doublenewline,R1`
332			`JSR raw_put_string`
333			`LDI 0x0ff,R7`
334			`SW R7,(SPIO)`
335			`LW 12(DBG),PC`
336			`RTN`
337
338			`; R0 is return address`
339			`; R1 is register ID`
340			`; R2 is register value to output`
341			`uart_put_reg_value:`
342			`SW R0,16(DBG)`
343			`SW R2,20(DBG)`
344			`SW R3,24(DBG)`
345			`MOV R1,R2`
346			`LDI 'u',R1`
347			`CMP 16,R2`
348			`LDILO.LT 's',R1`
349			`SUB.GE 16,R2`
350			`JSR raw_put_uart`
351			`LDI '0',R1`
352			`CMP 10,R2`
353			`LDILO.GE '1',R1`
354			`SUB.GE 10,R2`
355			`JSR raw_put_uart`
356			`MOV R2,R1`
357			`AND 15,R1`
358			`JSR get_hex`
359			`JSR raw_put_uart`
360			`LDI ':',R1`
361			`JSR raw_put_uart`
362			`LW 20(DBG),R2`
363			`LDI 8,R3`
364			`uart_put_loop:`
365			`MOV R2,R1`
366			`LSR 28,R1`
367			`LSL 4,R2`
368			`JSR get_hex`
369			`JSR raw_put_uart`
370			`SUB 1,R3`
371			`BNZ uart_put_loop`
372			`LDI newline, R1`
373			`JSR raw_put_string`
374			`LW 16(DBG),R0`
375			`LW 20(DBG),R2`
376			`LW 24(DBG),R3`
377			`RTN`
378
379			`uart_dump_mem_value:`
380			`; R0 = return address`
381			`; R1 = Memory address`
382			`; R2 = Memory Value`
383			`; Local: R3 = working value`
384			`SW R0,28(DBG)`
385			`MOV R1,R3 ; R3 = Memory address`
386			`MOV R2,R4 ; R4 = Memory Value`
387			`LDI memopenstr,R1`
388			`JSR raw_put_string`
389			`; Set up a loop to dump things`
390			`LSL 16,R3 ; Ignore the first 16 bits`
391			`LDI 4,R2 ; We're going to do four hex digits here`
392			`;`
393			`uart_put_mem_address_loop:`
394			`MOV R3,R1`
395			`LSR 28,R1`
396			`LSL 4,R3`
397			`JSR get_hex`
398			`JSR raw_put_uart`
399			`SUB 1,R2`
400			`BNZ uart_put_mem_address_loop`
401			`; Put some transition characters`
402			`LDI memmidstr,R1`
403			`JSR raw_put_string`
404
405			`; Set up a loop to dump the memory value now`
406			`LDI 8,R2`
407			`uart_put_mem_value_loop:`
408			`MOV R4,R1`
409			`LSR 28,R1`
410			`LSL 4,R4`
411			`JSR get_hex`
412			`JSR raw_put_uart`
413			`SUB 1,R2`
414			`BNZ uart_put_mem_value_loop`
415			`; Clear the line`
416			`LDI newline,R1`
417			`JSR raw_put_string`
418			`; And return from our subroutine`
419			`LW 28(DBG),R0`
420			`RTN`
421
422			`get_hex:`
423			`ADD 0x30,R1`
424			`CMP 0x3a,R1`
425			`ADD.GE 7,R1 ; Add 'A'-'0'-10`
426			`JMP R0`
427
428			`; R0 is the return address`
429			`; R1 is the string address`
430			`raw_put_string:`
431			`SW R0,36(DBG)`
432			`SW R2,40(DBG)`
433			`MOV R1,R2`
434			`raw_put_string_next:`
435			`LB (R2),R1`
436			`CMP 0,R1`
437			`LW.Z 36(DBG),R0`
438			`LW.Z 40(DBG),R2`
439			`RTN.Z`
440			`ADD 1,R2`
441			`MOV raw_put_string_next(PC),R0`
442			`BRA raw_put_uart`
443
444			`; R0 is return address,`
445			`; R1 is value to transmit`
446			`raw_put_uart:`
447			`SW R2,32(DBG)`
448			`LDI INT_UARTTX,R2`
449			`SW R2,(PIC) ; Clear the PIC, turn off interrupts, etc.`
450			`raw_put_uart_retest:`
451			`LW (PIC),R2`
452			`TEST INT_UARTTX,R2`
453			`BZ raw_put_uart_retest`
454			`SW R1,(UART)`
455			`LW 32(DBG),R2`
456			`JMP R0`
457
458			`.section .fixdata`
459			`DBG:`
460			`.int 0,0,0,0,0,0,0,0,0,0`
461
462			`.set INT_UARTRX, 0x040`
463			`.set INT_UARTTX, 0x080`
464			`.set PIC, 0x0400`
465			`.set BUSERR, 0x0404`
466			`.set TMRA, 0x0408`
467			`.set TMRB, 0x040c`
468			`.set PWM, 0x0410`
469			`.set SPIO, 0x0414`
470			`.set GPIO, 0x0418`
471			`.set UART, 0x041c`
472			`.set VERSION, 0x0420`
473			`.set SCOPE, 0x0800`
474			`.set SCOPED, 0x0804`
475			`.set RAM, 0x8000`
476			`.section .rodata`
477			`doublenewline:`
478			`.ascii "\r\n"`
479			`newline:`
480			`.asciz "\r\n"`
481			`buserr_header:`
482			`.string "BusErr: "`
483			`panicstr:`
484			`.string "Panic: \r\n"`
485			`memopenstr:`
486			`.string "M[0x"`
487			`memmidstr:`
488			`.string "]: "`
489			`gostr:`
490			`.string "Go!\r\n"`
491