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[/] [s6soc/] [trunk/] [sw/] [host/] [regdefs.cpp] - Blame information for rev 45

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1 8 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    regdefs.cpp
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//
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// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
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//
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// Purpose:     To give human readable names to the various registers available
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//              internal to the processor on the wishbone bus.  This file is
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//      primarily used for name to number translation within wbregs.cpp.
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//      All names for a given register are equivalent, save only that the
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//      register will always be identified by its first name in any output.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdio.h>
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#include <stdlib.h>
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#include <strings.h>
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#include <ctype.h>
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#include "regdefs.h"
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const   REGNAME raw_bregs[] = {
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        { R_VERSION,    "VERSION"               },
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        { R_ICONTROL,   "ICONTROL"              },
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        { R_ICONTROL,   "INT"                   },
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        { R_ICONTROL,   "PIC"                   },
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        { R_ICONTROL,   "INTC"                  },
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        { R_BUSERR,     "BUSERR"                },
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        { R_BUSERR,     "BUS"                   },
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        { R_ITIMERA,    "TMRA"                  },
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        { R_ITIMERB,    "TMRB"                  },
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        { R_PWM,        "PWMAUDIO"              },
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        { R_PWM,        "PWM"                   },
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        { R_PWM,        "PWMDATA"               },
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        { R_PWM,        "AUDIO"                 },
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        { R_SPIO,       "SPIO"                  },
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        { R_GPIO,       "GPIO"                  },
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        { R_UART,       "UART"                  },
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        { R_UART,       "UART-RX"               },
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        { R_UART,       "UARTRX"                },
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        { R_UART,       "RX"                    },
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        { R_UART,       "UART-TX"               },
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        { R_UART,       "UARTTX"                },
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        { R_UART,       "TX"                    },
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        //
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        { R_QSPI_EREG,  "QSPIEREG"              },
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        { R_QSPI_EREG,  "QSPIE"                 },
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        { R_QSPI_CREG,  "QSPICONF"              },
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        { R_QSPI_CREG,  "QSPIC"                 },
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        { R_QSPI_SREG,  "QSPISTAT"              },
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        { R_QSPI_SREG,  "QSPIS"                 },
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        { R_QSPI_IDREG, "QSPIID"                },
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        { R_QSPI_IDREG, "QSPII"                 },
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        //
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        // The real-time-clock registers have been removed
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        //      (they never fit in the core)
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        //
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        // The real-time-date register has been removed
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        //      (it never fit either)
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        //
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        // The wishbone scope
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        //
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        { R_SCOPE,      "SCOPE"                 },
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        { R_SCOPE,      "SCOP"                  },
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        { R_SCOPED,     "SCOPDATA"              },
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        { R_SCOPED,     "SCDATA"                },
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        { R_SCOPED,     "SCOPED"                },
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        { R_SCOPED,     "SCOPD"                 },
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        //
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        // The ICAPE interface registers have been removed.
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        //
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        { RAMBASE,      "MEM"                   },
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        { SPIFLASH,     "FLASH"                 }
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};
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#define RAW_NREGS       (sizeof(raw_bregs)/sizeof(bregs[0]))
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const   REGNAME *bregs = raw_bregs;
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const   int     NREGS = RAW_NREGS;
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unsigned        addrdecode(const char *v) {
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        if (isalpha(v[0])) {
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                for(int i=0; i<NREGS; i++)
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                        if (strcasecmp(v, bregs[i].m_name)==0)
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                                return bregs[i].m_addr;
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                fprintf(stderr, "Unknown register: %s\n", v);
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                exit(-2);
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        } else
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                return strtoul(v, NULL, 0);
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}
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const   char *addrname(const unsigned v) {
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        for(int i=0; i<NREGS; i++)
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                if (bregs[i].m_addr == v)
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                        return bregs[i].m_name;
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        return NULL;
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}
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