OpenCores
URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [sw/] [host/] [regdefs.cpp] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    regdefs.cpp
4
//
5
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
6
//
7
// Purpose:     To give human readable names to the various registers available
8
//              internal to the processor on the wishbone bus.  This file is
9
//      primarily used for name to number translation within wbregs.cpp.
10
//      All names for a given register are equivalent, save only that the
11
//      register will always be identified by its first name in any output.
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14
//              Gisselquist Technology, LLC
15
//
16
////////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// You should have received a copy of the GNU General Public License along
31
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
32
// target there if the PDF file isn't present.)  If not, see
33
// <http://www.gnu.org/licenses/> for a copy.
34
//
35
// License:     GPL, v3, as defined and found on www.gnu.org,
36
//              http://www.gnu.org/licenses/gpl.html
37
//
38
//
39
////////////////////////////////////////////////////////////////////////////////
40
//
41
//
42
#include <stdio.h>
43
#include <stdlib.h>
44
#include <strings.h>
45
#include <ctype.h>
46
#include "regdefs.h"
47
 
48
const   REGNAME raw_bregs[] = {
49
        { R_VERSION,    "VERSION"               },
50
        { R_ICONTROL,   "ICONTROL"              },
51
        { R_ICONTROL,   "INT"                   },
52
        { R_ICONTROL,   "PIC"                   },
53
        { R_ICONTROL,   "INTC"                  },
54
        { R_BUSERR,     "BUSERR"                },
55
        { R_BUSERR,     "BUS"                   },
56
        { R_ITIMERA,    "TMRA"                  },
57
        { R_ITIMERB,    "TMRB"                  },
58
        { R_PWM,        "PWMAUDIO"              },
59
        { R_PWM,        "PWM"                   },
60
        { R_PWM,        "PWMDATA"               },
61
        { R_PWM,        "AUDIO"                 },
62
        { R_SPIO,       "SPIO"                  },
63
        { R_GPIO,       "GPIO"                  },
64
        { R_UART,       "UART"                  },
65
        { R_UART,       "UART-RX"               },
66
        { R_UART,       "UARTRX"                },
67
        { R_UART,       "RX"                    },
68
        { R_UART,       "UART-TX"               },
69
        { R_UART,       "UARTTX"                },
70
        { R_UART,       "TX"                    },
71
        //
72
        { R_QSPI_EREG,  "QSPIEREG"              },
73
        { R_QSPI_EREG,  "QSPIE"                 },
74
        { R_QSPI_CREG,  "QSPICONF"              },
75
        { R_QSPI_CREG,  "QSPIC"                 },
76
        { R_QSPI_SREG,  "QSPISTAT"              },
77
        { R_QSPI_SREG,  "QSPIS"                 },
78
        { R_QSPI_IDREG, "QSPIID"                },
79
        { R_QSPI_IDREG, "QSPII"                 },
80
        //
81
        { R_CLOCK,      "CLOCK"                 },
82
        { R_CLOCK,      "TIME"                  },
83
        { R_TIMER,      "TIMER"                 },
84
        { R_STOPWATCH,  "STOPWACH"              },
85
        { R_STOPWATCH,  "STOPWATCH"             },
86
        { R_CKALARM,    "CKALARM"               },
87
        { R_CKALARM,    "ALARM"                 },
88
        // { R_DATE,    "DATE"                  },
89
        // Scopes are defined and come and go.  Be aware, therefore, not all
90
        // of these scopes may be defined at the same time.
91
        { R_SCOPE,      "SCOPE"                 },
92
        { R_SCOPE,      "SCOP"                  },
93
        { R_SCOPED,     "SCOPDATA"              },
94
        { R_SCOPED,     "SCDATA"                },
95
        { R_SCOPED,     "SCOPED"                },
96
        { R_SCOPED,     "SCOPD"                 },
97
        //
98
        // For working with the ICAPE interface ... if I can ever get a
99
        // testing environment suitable to prove that it works.
100
        //
101
        { R_CFG_CRC,    "FPGACRC"               },
102
        { R_CFG_FAR_MAJ, "FPGAFARH"             },
103
        { R_CFG_FAR_MIN, "FPGAFARL"             },
104
        { R_CFG_FDRI,   "FPGAFDRI"              },
105
        { R_CFG_FDRO,   "FPGAFDRO"              },
106
        { R_CFG_CMD,    "FPGACMD"               },
107
        { R_CFG_CTL,    "FPGACTL"               },
108
        { R_CFG_MASK,   "FPGAMASK"              },
109
        { R_CFG_STAT,   "FPGASTAT"              },
110
        { R_CFG_LOUT,   "FPGALOUT"              },
111
        { R_CFG_COR1,   "FPGACOR1"              },
112
        { R_CFG_COR2,   "FPGACOR2"              },
113
        { R_CFG_PWRDN,  "FPGAPWRDN"             },
114
        { R_CFG_FLR,    "FPGAFLR"               },
115
        { R_CFG_IDCODE, "FPGAIDCODE"            },
116
        { R_CFG_CWDT,   "FPGACWDT"              },
117
        { R_CFG_HCOPT,  "FPGAHCOPT"             },
118
        { R_CFG_CSBO,   "FPGACSBO"              },
119
        { R_CFG_GEN1,   "FPGAGEN1"              },
120
        { R_CFG_GEN2,   "FPGAGEN2"              },
121
        { R_CFG_GEN3,   "FPGAGEN3"              },
122
        { R_CFG_GEN4,   "FPGAGEN4"              },
123
        { R_CFG_GEN5,   "FPGAGEN5"              },
124
        { R_CFG_MODE,   "FPGAMODE"              },
125
        { R_CFG_GWE,    "FPGAGWE"               },
126
        { R_CFG_GTS,    "FPGAGTS"               },
127
        { R_CFG_MFWR,   "FPGAMFWR"              },
128
        { R_CFG_CCLK,   "FPGACCLK"              },
129
        { R_CFG_SEU,    "FPGASEU"               },
130
        { R_CFG_EXP,    "FPGAEXP"               },
131
        { R_CFG_RDBK,   "FPGARDBK"              },
132
        { R_CFG_BOOTSTS, "BOOTSTS"              },
133
        { R_CFG_EYE,    "FPGAEYE"               },
134
        { R_CFG_CBC,    "FPGACBC"               },
135
        //
136
        { RAMBASE,      "MEM"                   },
137
        { SPIFLASH,     "FLASH"                 }
138
};
139
 
140
#define RAW_NREGS       (sizeof(raw_bregs)/sizeof(bregs[0]))
141
 
142
const   REGNAME *bregs = raw_bregs;
143
const   int     NREGS = RAW_NREGS;
144
 
145
unsigned        addrdecode(const char *v) {
146
        if (isalpha(v[0])) {
147
                for(int i=0; i<NREGS; i++)
148
                        if (strcasecmp(v, bregs[i].m_name)==0)
149
                                return bregs[i].m_addr;
150
                fprintf(stderr, "Unknown register: %s\n", v);
151
                exit(-2);
152
        } else
153
                return strtoul(v, NULL, 0);
154
}
155
 
156
const   char *addrname(const unsigned v) {
157
        for(int i=0; i<NREGS; i++)
158
                if (bregs[i].m_addr == v)
159
                        return bregs[i].m_name;
160
        return NULL;
161
}
162
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.