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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Blame information for rev 36

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1 3 dinesha
/*********************************************************************
2
 
3
  SDRAM Controller Core File
4
 
5
  This file is part of the sdram controller project
6
  http://www.opencores.org/cores/sdr_ctrl/
7
 
8
  Description: SDRAM Controller Core Module
9
    2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
10
    This block integrate following sub modules
11
 
12
    sdrc_bs_convert
13 33 dinesha
        convert the system side 32 bit into equvailent 8/16/32 SDR format
14 3 dinesha
    sdrc_req_gen
15
        This module takes requests from the app, chops them to burst booundaries
16
        if wrap=0, decodes the bank and passe the request to bank_ctl
17
   sdrc_xfr_ctl
18
      This module takes requests from sdr_bank_ctl, runs the transfer and
19
      controls data flow to/from the app. At the end of the transfer it issues a
20
      burst terminate if not at the end of a burst and another command to this
21
      bank is not available.
22
 
23
   sdrc_bank_ctl
24
      This module takes requests from sdr_req_gen, checks for page hit/miss and
25
      issues precharge/activate commands and then passes the request to
26
      sdr_xfr_ctl.
27
 
28
 
29
  Assumption: SDRAM Pads should be placed near to this module. else
30
  user should add a FF near the pads
31
 
32
  To Do:
33
    nothing
34
 
35
  Author(s):
36
      - Dinesh Annayya, dinesha@opencores.org
37
  Version  : 1.0 - 8th Jan 2012
38 16 dinesha
                Initial version with 16/32 Bit SDRAM Support
39
           : 1.1 - 24th Jan 2012
40
                 8 Bit SDRAM Support is added
41 3 dinesha
 
42
 
43
 Copyright (C) 2000 Authors and OPENCORES.ORG
44
 
45
 This source file may be used and distributed without
46
 restriction provided that this copyright statement is not
47
 removed from the file and that any derivative work contains
48
 the original copyright notice and the associated disclaimer.
49
 
50
 This source file is free software; you can redistribute it
51
 and/or modify it under the terms of the GNU Lesser General
52
 Public License as published by the Free Software Foundation;
53
 either version 2.1 of the License, or (at your option) any
54
later version.
55
 
56
 This source is distributed in the hope that it will be
57
 useful, but WITHOUT ANY WARRANTY; without even the implied
58
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
59
 PURPOSE.  See the GNU Lesser General Public License for more
60
 details.
61
 
62
 You should have received a copy of the GNU Lesser General
63
 Public License along with this source; if not, download it
64
 from http://www.opencores.org/lgpl.shtml
65
 
66
*******************************************************************/
67
 
68
 
69
`include "sdrc.def"
70
module sdrc_core
71
           (
72 4 dinesha
                clk,
73
                pad_clk,
74 3 dinesha
                reset_n,
75
                sdr_width,
76 13 dinesha
                cfg_colbits,
77 3 dinesha
 
78
                /* Request from app */
79
                app_req,                // Transfer Request
80
                app_req_addr,           // SDRAM Address
81
                app_req_addr_mask,      // Address mask for queue wrap
82
                app_req_len,            // Burst Length (in 16 bit words)
83
                app_req_wrap,           // Wrap mode request (xfr_len = 4)
84
                app_req_wr_n,           // 0 => Write request, 1 => read req
85
                app_req_ack,            // Request has been accepted
86
                sdr_core_busy_n,                // OK to arbitrate next request
87
                cfg_req_depth,          //how many req. buffer should hold
88
 
89
                app_wr_data,
90
                app_wr_en_n,
91
                app_rd_data,
92
                app_rd_valid,
93 31 dinesha
                app_last_rd,
94 3 dinesha
                app_wr_next_req,
95
                sdr_init_done,
96
                app_req_dma_last,
97
 
98
                /* Interface to SDRAMs */
99
                sdr_cs_n,
100
                sdr_cke,
101
                sdr_ras_n,
102
                sdr_cas_n,
103
                sdr_we_n,
104
                sdr_dqm,
105
                sdr_ba,
106
                sdr_addr,
107
                pad_sdr_din,
108
                sdr_dout,
109
                sdr_den_n,
110
 
111
                /* Parameters */
112
                cfg_sdr_en,
113
                cfg_sdr_mode_reg,
114
                cfg_sdr_tras_d,
115
                cfg_sdr_trp_d,
116
                cfg_sdr_trcd_d,
117
                cfg_sdr_cas,
118
                cfg_sdr_trcar_d,
119
                cfg_sdr_twr_d,
120
                cfg_sdr_rfsh,
121
                cfg_sdr_rfmax);
122
 
123
parameter  APP_AW   = 30;  // Application Address Width
124
parameter  APP_DW   = 32;  // Application Data Width 
125
parameter  APP_BW   = 4;   // Application Byte Width
126
parameter  APP_RW   = 9;   // Application Request Width
127
 
128
parameter  SDR_DW   = 16;  // SDR Data Width 
129
parameter  SDR_BW   = 2;   // SDR Byte Width
130
 
131
 
132
//-----------------------------------------------
133
// Global Variable
134
// ----------------------------------------------
135 4 dinesha
input                   clk                 ; // SDRAM Clock 
136
input                   pad_clk             ; // SDRAM Clock from Pad, used for registering Read Data
137 3 dinesha
input                   reset_n             ; // Reset Signal
138 16 dinesha
input [1:0]             sdr_width           ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
139 13 dinesha
input [1:0]             cfg_colbits         ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
140 3 dinesha
 
141 13 dinesha
 
142 3 dinesha
//------------------------------------------------
143
// Request from app
144
//------------------------------------------------
145
input                   app_req             ; // Application Request
146
input [APP_AW-1:0]       app_req_addr        ; // Address 
147
input [APP_AW-2:0]      app_req_addr_mask   ; // Address Mask
148
input                   app_req_wr_n        ; // 0 - Write, 1 - Read
149
input                   app_req_wrap        ; // Address Wrap
150
output                  app_req_ack         ; // Application Request Ack
151
output                  sdr_core_busy_n     ; // 0 - busy, 1 - free
152
 
153
input [APP_DW-1:0]       app_wr_data         ; // Write Data
154
output                  app_wr_next_req     ; // Next Write Data Request
155
input [APP_BW-1:0]       app_wr_en_n         ; // Byte wise Write Enable
156
output [APP_DW-1:0]      app_rd_data         ; // Read Data
157
output                  app_rd_valid        ; // Read Valid
158 31 dinesha
output                  app_last_rd         ; // Last Read Transfer of a given Burst
159 3 dinesha
 
160
//------------------------------------------------
161
// Interface to SDRAMs
162
//------------------------------------------------
163
output                  sdr_cke             ; // SDRAM CKE
164
output                  sdr_cs_n            ; // SDRAM Chip Select
165
output                  sdr_ras_n           ; // SDRAM ras
166
output                  sdr_cas_n           ; // SDRAM cas
167
output                  sdr_we_n            ; // SDRAM write enable
168
output [SDR_BW-1:0]      sdr_dqm             ; // SDRAM Data Mask
169
output [1:0]             sdr_ba              ; // SDRAM Bank Enable
170
output [11:0]            sdr_addr            ; // SDRAM Address
171
input [SDR_DW-1:0]       pad_sdr_din         ; // SDRA Data Input
172
output [SDR_DW-1:0]      sdr_dout            ; // SDRAM Data Output
173
output [SDR_BW-1:0]      sdr_den_n           ; // SDRAM Data Output enable
174
 
175
//------------------------------------------------
176
// Configuration Parameter
177
//------------------------------------------------
178 13 dinesha
output                  sdr_init_done       ; // Indicate SDRAM Initialisation Done
179
input [3:0]              cfg_sdr_tras_d      ; // Active to precharge delay
180
input [3:0]             cfg_sdr_trp_d       ; // Precharge to active delay
181
input [3:0]             cfg_sdr_trcd_d      ; // Active to R/W delay
182
input                   cfg_sdr_en          ; // Enable SDRAM controller
183
input [1:0]              cfg_req_depth       ; // Maximum Request accepted by SDRAM controller
184
input [APP_RW-1:0]       app_req_len         ; // Application Burst Request length in 32 bit 
185 3 dinesha
input [11:0]             cfg_sdr_mode_reg    ;
186 13 dinesha
input [2:0]              cfg_sdr_cas         ; // SDRAM CAS Latency
187
input [3:0]              cfg_sdr_trcar_d     ; // Auto-refresh period
188
input [3:0]             cfg_sdr_twr_d       ; // Write recovery delay
189 3 dinesha
input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
190
input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
191
input                   app_req_dma_last;    // this signal should close the bank
192
 
193
/****************************************************************************/
194
// Internal Nets
195
 
196
// SDR_REQ_GEN
197
wire                    r2x_idle, app_req_ack,app_req_ack_int;
198
wire                    app_req_dma_last_int;
199
wire                    r2b_req, r2b_start, r2b_last, r2b_write;
200
wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
201
wire [1:0]               r2b_ba;
202
wire [11:0]              r2b_raddr;
203
wire [11:0]              r2b_caddr;
204
wire [APP_RW-1:0]        r2b_len;
205
 
206
// SDR BANK CTL
207
wire                    b2r_ack, b2x_idle;
208
wire                    b2x_req, b2x_start, b2x_last, b2x_tras_ok;
209
wire [`SDR_REQ_ID_W-1:0]b2x_id;
210
wire [1:0]               b2x_ba;
211
wire                    b2x_ba_last;
212
wire [11:0]              b2x_addr;
213
wire [APP_RW-1:0]        b2x_len;
214
wire [1:0]               b2x_cmd;
215
 
216
// SDR_XFR_CTL
217
wire                    x2b_ack;
218
wire [3:0]               x2b_pre_ok;
219
wire                    x2b_refresh, x2b_act_ok, x2b_rdok, x2b_wrok;
220 31 dinesha
wire                    xfr_rdstart, app_last_rd;
221 3 dinesha
wire                    xfr_wrstart, xfr_wrlast;
222
wire [`SDR_REQ_ID_W-1:0]xfr_id;
223
wire [APP_DW-1:0]        app_rd_data;
224
wire                    app_wr_next_req, app_rd_valid;
225
wire                    sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n;
226
wire [SDR_BW-1:0]        sdr_dqm;
227
wire [1:0]               sdr_ba;
228
wire [11:0]              sdr_addr;
229
wire [SDR_DW-1:0]        sdr_dout;
230
wire [SDR_DW-1:0]        sdr_dout_int;
231
wire [SDR_BW-1:0]        sdr_den_n;
232
wire [SDR_BW-1:0]        sdr_den_n_int;
233
 
234
wire [1:0]               xfr_bank_sel;
235
 
236
wire [APP_AW:0]          app_req_addr_int;
237
wire [APP_AW-1:0]        app_req_addr;
238
wire [APP_RW-1:0]        app_req_len_int;
239
wire [APP_RW-1:0]        app_req_len;
240
 
241
wire [APP_DW-1:0]        app_wr_data;
242
wire [SDR_DW-1:0]        add_wr_data_int;
243
wire [APP_BW-1:0]        app_wr_en_n;
244
wire [SDR_BW-1:0]        app_wr_en_n_int;
245
 
246
//wire [31:0] app_rd_data;
247
wire [SDR_DW-1:0]        app_rd_data_int;
248
 
249
//
250
wire                     app_req_int;
251
wire                     r2b_wrap;
252
wire                     b2r_arb_ok;
253
wire                     b2x_wrap;
254
wire                     app_wr_next_int;
255
wire                     app_rd_valid_int;
256
 
257
// synopsys translate_off 
258
   wire [3:0]           sdr_cmd;
259
   assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
260
// synopsys translate_on 
261
 
262 16 dinesha
   assign sdr_den_n = sdr_den_n_int ;
263
   assign sdr_dout  = sdr_dout_int ;
264 3 dinesha
 
265
 
266 23 dinesha
// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
267
// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
268
// register w.r.t pad sdram clk
269
reg [SDR_DW-1:0] pad_sdr_din1;
270
reg [SDR_DW-1:0] pad_sdr_din2;
271
always@(posedge pad_clk) begin
272
   pad_sdr_din1 <= pad_sdr_din;
273
end
274
 
275
always@(posedge clk) begin
276
   pad_sdr_din2 <= pad_sdr_din1;
277
end
278
 
279 3 dinesha
   /****************************************************************************/
280
   // Instantiate sdr_req_gen
281
   // This module takes requests from the app, chops them to burst booundaries
282
   // if wrap=0, decodes the bank and passe the request to bank_ctl
283
 
284 9 dinesha
sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen (
285 4 dinesha
          .clk                (clk          ),
286 3 dinesha
          .reset_n            (reset_n            ),
287 13 dinesha
          .cfg_colbits        (cfg_colbits        ),
288 3 dinesha
 
289
        /* Request from app */
290
          .r2x_idle           (r2x_idle           ),
291
          .req                (app_req_int        ),
292
          .req_id             (4'b0               ),
293
          .req_addr           (app_req_addr_int   ),
294
          .req_addr_mask      (app_req_addr_mask  ),
295
          .req_len            (app_req_len_int    ),
296
          .req_wrap           (app_req_wrap       ),
297
          .req_wr_n           (app_req_wr_n       ),
298
          .req_ack            (app_req_ack_int      ),
299
          .sdr_core_busy_n    (sdr_core_busy_n    ),
300
 
301
       /* Req to bank_ctl */
302
          .r2b_req            (r2b_req            ),
303
          .r2b_req_id         (r2b_req_id         ),
304
          .r2b_start          (r2b_start          ),
305
          .r2b_last           (r2b_last           ),
306
          .r2b_wrap           (r2b_wrap           ),
307
          .r2b_ba             (r2b_ba             ),
308
          .r2b_raddr          (r2b_raddr          ),
309
          .r2b_caddr          (r2b_caddr          ),
310
          .r2b_len            (r2b_len            ),
311
          .r2b_write          (r2b_write          ),
312
          .b2r_ack            (b2r_ack            ),
313
          .b2r_arb_ok         (b2r_arb_ok         ),
314
          .sdr_width          (sdr_width          ),
315
          .sdr_init_done      (sdr_init_done      )
316
     );
317
 
318
   /****************************************************************************/
319
   // Instantiate sdr_bank_ctl
320
   // This module takes requests from sdr_req_gen, checks for page hit/miss and
321
   // issues precharge/activate commands and then passes the request to
322
   // sdr_xfr_ctl. 
323
 
324 9 dinesha
sdrc_bank_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bank_ctl (
325 4 dinesha
          .clk                (clk          ),
326 3 dinesha
          .reset_n            (reset_n            ),
327
          .a2b_req_depth      (cfg_req_depth      ),
328
 
329
      /* Req from req_gen */
330
          .r2b_req            (r2b_req            ),
331
          .r2b_req_id         (r2b_req_id         ),
332
          .r2b_start          (r2b_start          ),
333
          .r2b_last           (r2b_last           ),
334
          .r2b_wrap           (r2b_wrap           ),
335
          .r2b_ba             (r2b_ba             ),
336
          .r2b_raddr          (r2b_raddr          ),
337
          .r2b_caddr          (r2b_caddr          ),
338
          .r2b_len            (r2b_len            ),
339
          .r2b_write          (r2b_write          ),
340
          .b2r_arb_ok         (b2r_arb_ok         ),
341
          .b2r_ack            (b2r_ack            ),
342
 
343
      /* Transfer request to xfr_ctl */
344
          .b2x_idle           (b2x_idle           ),
345
          .b2x_req            (b2x_req            ),
346
          .b2x_start          (b2x_start          ),
347
          .b2x_last           (b2x_last           ),
348
          .b2x_wrap           (b2x_wrap           ),
349
          .b2x_id             (b2x_id             ),
350
          .b2x_ba             (b2x_ba             ),
351
          .b2x_addr           (b2x_addr           ),
352
          .b2x_len            (b2x_len            ),
353
          .b2x_cmd            (b2x_cmd            ),
354
          .x2b_ack            (x2b_ack            ),
355
 
356
      /* Status from xfr_ctl */
357
          .b2x_tras_ok        (b2x_tras_ok        ),
358
          .x2b_refresh        (x2b_refresh        ),
359
          .x2b_pre_ok         (x2b_pre_ok         ),
360
          .x2b_act_ok         (x2b_act_ok         ),
361
          .x2b_rdok           (x2b_rdok           ),
362
          .x2b_wrok           (x2b_wrok           ),
363
 
364
      /* for generate cuurent xfr address msb */
365
          .sdr_req_norm_dma_last(app_req_dma_last_int),
366
          .xfr_bank_sel       (xfr_bank_sel       ),
367
 
368
       /* SDRAM Timing */
369
          .tras_delay         (cfg_sdr_tras_d     ),
370
          .trp_delay          (cfg_sdr_trp_d      ),
371
          .trcd_delay         (cfg_sdr_trcd_d     )
372
      );
373
 
374
   /****************************************************************************/
375
   // Instantiate sdr_xfr_ctl
376
   // This module takes requests from sdr_bank_ctl, runs the transfer and
377
   // controls data flow to/from the app. At the end of the transfer it issues a
378
   // burst terminate if not at the end of a burst and another command to this
379
   // bank is not available.
380
 
381 9 dinesha
sdrc_xfr_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_xfr_ctl (
382 4 dinesha
          .clk                (clk          ),
383 3 dinesha
          .reset_n            (reset_n            ),
384
 
385
      /* Transfer request from bank_ctl */
386
          .r2x_idle           (r2x_idle           ),
387
          .b2x_idle           (b2x_idle           ),
388
          .b2x_req            (b2x_req            ),
389
          .b2x_start          (b2x_start          ),
390
          .b2x_last           (b2x_last           ),
391
          .b2x_wrap           (b2x_wrap           ),
392
          .b2x_id             (b2x_id             ),
393
          .b2x_ba             (b2x_ba             ),
394
          .b2x_addr           (b2x_addr           ),
395
          .b2x_len            (b2x_len            ),
396
          .b2x_cmd            (b2x_cmd            ),
397
          .x2b_ack            (x2b_ack            ),
398
 
399
       /* Status to bank_ctl, req_gen */
400
          .b2x_tras_ok        (b2x_tras_ok        ),
401
          .x2b_refresh        (x2b_refresh        ),
402
          .x2b_pre_ok         (x2b_pre_ok         ),
403
          .x2b_act_ok         (x2b_act_ok         ),
404
          .x2b_rdok           (x2b_rdok           ),
405
          .x2b_wrok           (x2b_wrok           ),
406
 
407
       /* SDRAM I/O */
408
          .sdr_cs_n           (sdr_cs_n           ),
409
          .sdr_cke            (sdr_cke            ),
410
          .sdr_ras_n          (sdr_ras_n          ),
411
          .sdr_cas_n          (sdr_cas_n          ),
412
          .sdr_we_n           (sdr_we_n           ),
413
          .sdr_dqm            (sdr_dqm            ),
414
          .sdr_ba             (sdr_ba             ),
415
          .sdr_addr           (sdr_addr           ),
416 23 dinesha
          .sdr_din            (pad_sdr_din2       ),
417 3 dinesha
          .sdr_dout           (sdr_dout_int       ),
418
          .sdr_den_n          (sdr_den_n_int      ),
419
 
420
      /* Data Flow to the app */
421
          .x2a_rdstart        (xfr_rdstart        ),
422
          .x2a_wrstart        (xfr_wrstart        ),
423
          .x2a_id             (xfr_id             ),
424 31 dinesha
          .x2a_rdlast         (app_last_rd         ),
425 3 dinesha
          .x2a_wrlast         (xfr_wrlast         ),
426
          .app_wrdt           (add_wr_data_int    ),
427 4 dinesha
          .app_wren_n         (app_wr_en_n_int    ),
428 3 dinesha
          .x2a_wrnext         (app_wr_next_int    ),
429
          .x2a_rddt           (app_rd_data_int    ),
430
          .x2a_rdok           (app_rd_valid_int   ),
431
          .sdr_init_done      (sdr_init_done      ),
432
 
433
      /* SDRAM Parameters */
434
          .sdram_enable       (cfg_sdr_en         ),
435
          .sdram_mode_reg     (cfg_sdr_mode_reg   ),
436
 
437
      /* current xfr bank */
438
          .xfr_bank_sel       (xfr_bank_sel       ),
439
 
440
      /* SDRAM Timing */
441
          .cas_latency        (cfg_sdr_cas        ),
442
          .trp_delay          (cfg_sdr_trp_d      ),
443
          .trcar_delay        (cfg_sdr_trcar_d    ),
444
          .twr_delay          (cfg_sdr_twr_d      ),
445
          .rfsh_time          (cfg_sdr_rfsh       ),
446
          .rfsh_rmax          (cfg_sdr_rfmax      )
447
    );
448
 
449 33 dinesha
   /****************************************************************************/
450
   // Instantiate sdr_bs_convert
451
   //    This model handle the bus with transaltion from application layer to
452
   //       8/16/32 SDRAM Memory format
453
   //     During Write Phase, this block split the data as per SDRAM Width
454
   //     During Read Phase, This block does the re-packing based on SDRAM
455
   //     Width
456
   //---------------------------------------------------------------------------
457 9 dinesha
sdrc_bs_convert #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bs_convert (
458 4 dinesha
          .clk                (clk          ),
459 3 dinesha
          .reset_n            (reset_n            ),
460
          .sdr_width          (sdr_width          ),
461
 
462
          .app_req_addr       (app_req_addr       ),
463
          .app_req_addr_int   (app_req_addr_int   ),
464
          .app_req_len        (app_req_len        ),
465
          .app_req_len_int    (app_req_len_int    ),
466
          .app_sdr_req        (app_req            ),
467
          .app_sdr_req_int    (app_req_int        ),
468
          .app_req_dma_last   (app_req_dma_last   ),
469
          .app_req_dma_last_int(app_req_dma_last_int),
470
          .app_req_wr_n       (app_req_wr_n       ),
471 4 dinesha
          .app_req_ack_int    (app_req_ack_int    ),
472 3 dinesha
          .app_req_ack        (app_req_ack        ),
473
 
474
          .app_wr_data        (app_wr_data        ),
475
          .app_wr_data_int    (add_wr_data_int    ),
476
          .app_wr_en_n        (app_wr_en_n        ),
477
          .app_wr_en_n_int    (app_wr_en_n_int    ),
478
          .app_wr_next_int    (app_wr_next_int    ),
479
          .app_wr_next        (app_wr_next_req    ),
480
 
481
          .app_rd_data_int    (app_rd_data_int    ),
482
          .app_rd_data        (app_rd_data        ),
483
          .app_rd_valid_int   (app_rd_valid_int   ),
484
          .app_rd_valid       (app_rd_valid       )
485
       );
486
 
487
endmodule // sdrc_core

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