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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_core.v] - Blame information for rev 46

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1 3 dinesha
/*********************************************************************
2
 
3
  SDRAM Controller Core File
4
 
5
  This file is part of the sdram controller project
6
  http://www.opencores.org/cores/sdr_ctrl/
7
 
8
  Description: SDRAM Controller Core Module
9
    2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
10
    This block integrate following sub modules
11
 
12
    sdrc_bs_convert
13 33 dinesha
        convert the system side 32 bit into equvailent 8/16/32 SDR format
14 3 dinesha
    sdrc_req_gen
15
        This module takes requests from the app, chops them to burst booundaries
16
        if wrap=0, decodes the bank and passe the request to bank_ctl
17
   sdrc_xfr_ctl
18
      This module takes requests from sdr_bank_ctl, runs the transfer and
19
      controls data flow to/from the app. At the end of the transfer it issues a
20
      burst terminate if not at the end of a burst and another command to this
21
      bank is not available.
22
 
23
   sdrc_bank_ctl
24
      This module takes requests from sdr_req_gen, checks for page hit/miss and
25
      issues precharge/activate commands and then passes the request to
26
      sdr_xfr_ctl.
27
 
28
 
29
  Assumption: SDRAM Pads should be placed near to this module. else
30
  user should add a FF near the pads
31
 
32
  To Do:
33
    nothing
34
 
35
  Author(s):
36
      - Dinesh Annayya, dinesha@opencores.org
37 44 dinesha
  Version  : 0.0 - 8th Jan 2012
38 16 dinesha
                Initial version with 16/32 Bit SDRAM Support
39 44 dinesha
           : 0.1 - 24th Jan 2012
40 16 dinesha
                 8 Bit SDRAM Support is added
41 44 dinesha
             0.2 - 2nd Feb 2012
42
                 Improved the command pipe structure to accept up-to 4 command of different bank.
43 3 dinesha
 
44
 
45
 Copyright (C) 2000 Authors and OPENCORES.ORG
46
 
47
 This source file may be used and distributed without
48
 restriction provided that this copyright statement is not
49
 removed from the file and that any derivative work contains
50
 the original copyright notice and the associated disclaimer.
51
 
52
 This source file is free software; you can redistribute it
53
 and/or modify it under the terms of the GNU Lesser General
54
 Public License as published by the Free Software Foundation;
55
 either version 2.1 of the License, or (at your option) any
56
later version.
57
 
58
 This source is distributed in the hope that it will be
59
 useful, but WITHOUT ANY WARRANTY; without even the implied
60
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
61
 PURPOSE.  See the GNU Lesser General Public License for more
62
 details.
63
 
64
 You should have received a copy of the GNU Lesser General
65
 Public License along with this source; if not, download it
66
 from http://www.opencores.org/lgpl.shtml
67
 
68
*******************************************************************/
69
 
70
 
71 37 dinesha
`include "sdrc_define.v"
72 3 dinesha
module sdrc_core
73
           (
74 4 dinesha
                clk,
75
                pad_clk,
76 3 dinesha
                reset_n,
77
                sdr_width,
78 13 dinesha
                cfg_colbits,
79 3 dinesha
 
80
                /* Request from app */
81
                app_req,                // Transfer Request
82
                app_req_addr,           // SDRAM Address
83
                app_req_len,            // Burst Length (in 16 bit words)
84
                app_req_wrap,           // Wrap mode request (xfr_len = 4)
85
                app_req_wr_n,           // 0 => Write request, 1 => read req
86
                app_req_ack,            // Request has been accepted
87
                sdr_core_busy_n,                // OK to arbitrate next request
88
                cfg_req_depth,          //how many req. buffer should hold
89
 
90
                app_wr_data,
91
                app_wr_en_n,
92 45 dinesha
                app_last_wr,
93
 
94 3 dinesha
                app_rd_data,
95
                app_rd_valid,
96 31 dinesha
                app_last_rd,
97 3 dinesha
                app_wr_next_req,
98
                sdr_init_done,
99
                app_req_dma_last,
100
 
101
                /* Interface to SDRAMs */
102
                sdr_cs_n,
103
                sdr_cke,
104
                sdr_ras_n,
105
                sdr_cas_n,
106
                sdr_we_n,
107
                sdr_dqm,
108
                sdr_ba,
109
                sdr_addr,
110
                pad_sdr_din,
111
                sdr_dout,
112
                sdr_den_n,
113
 
114
                /* Parameters */
115
                cfg_sdr_en,
116
                cfg_sdr_mode_reg,
117
                cfg_sdr_tras_d,
118
                cfg_sdr_trp_d,
119
                cfg_sdr_trcd_d,
120
                cfg_sdr_cas,
121
                cfg_sdr_trcar_d,
122
                cfg_sdr_twr_d,
123
                cfg_sdr_rfsh,
124
                cfg_sdr_rfmax);
125
 
126
parameter  APP_AW   = 30;  // Application Address Width
127
parameter  APP_DW   = 32;  // Application Data Width 
128
parameter  APP_BW   = 4;   // Application Byte Width
129
parameter  APP_RW   = 9;   // Application Request Width
130
 
131
parameter  SDR_DW   = 16;  // SDR Data Width 
132
parameter  SDR_BW   = 2;   // SDR Byte Width
133
 
134
 
135
//-----------------------------------------------
136
// Global Variable
137
// ----------------------------------------------
138 4 dinesha
input                   clk                 ; // SDRAM Clock 
139
input                   pad_clk             ; // SDRAM Clock from Pad, used for registering Read Data
140 3 dinesha
input                   reset_n             ; // Reset Signal
141 16 dinesha
input [1:0]             sdr_width           ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
142 13 dinesha
input [1:0]             cfg_colbits         ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
143 3 dinesha
 
144 13 dinesha
 
145 3 dinesha
//------------------------------------------------
146
// Request from app
147
//------------------------------------------------
148
input                   app_req             ; // Application Request
149
input [APP_AW-1:0]       app_req_addr        ; // Address 
150
input                   app_req_wr_n        ; // 0 - Write, 1 - Read
151
input                   app_req_wrap        ; // Address Wrap
152
output                  app_req_ack         ; // Application Request Ack
153
output                  sdr_core_busy_n     ; // 0 - busy, 1 - free
154
 
155
input [APP_DW-1:0]       app_wr_data         ; // Write Data
156
output                  app_wr_next_req     ; // Next Write Data Request
157
input [APP_BW-1:0]       app_wr_en_n         ; // Byte wise Write Enable
158 45 dinesha
output                  app_last_wr         ; // Last Write trannsfer of a given Burst
159 3 dinesha
output [APP_DW-1:0]      app_rd_data         ; // Read Data
160
output                  app_rd_valid        ; // Read Valid
161 31 dinesha
output                  app_last_rd         ; // Last Read Transfer of a given Burst
162 3 dinesha
 
163
//------------------------------------------------
164
// Interface to SDRAMs
165
//------------------------------------------------
166
output                  sdr_cke             ; // SDRAM CKE
167
output                  sdr_cs_n            ; // SDRAM Chip Select
168
output                  sdr_ras_n           ; // SDRAM ras
169
output                  sdr_cas_n           ; // SDRAM cas
170
output                  sdr_we_n            ; // SDRAM write enable
171
output [SDR_BW-1:0]      sdr_dqm             ; // SDRAM Data Mask
172
output [1:0]             sdr_ba              ; // SDRAM Bank Enable
173
output [11:0]            sdr_addr            ; // SDRAM Address
174
input [SDR_DW-1:0]       pad_sdr_din         ; // SDRA Data Input
175
output [SDR_DW-1:0]      sdr_dout            ; // SDRAM Data Output
176
output [SDR_BW-1:0]      sdr_den_n           ; // SDRAM Data Output enable
177
 
178
//------------------------------------------------
179
// Configuration Parameter
180
//------------------------------------------------
181 13 dinesha
output                  sdr_init_done       ; // Indicate SDRAM Initialisation Done
182
input [3:0]              cfg_sdr_tras_d      ; // Active to precharge delay
183
input [3:0]             cfg_sdr_trp_d       ; // Precharge to active delay
184
input [3:0]             cfg_sdr_trcd_d      ; // Active to R/W delay
185
input                   cfg_sdr_en          ; // Enable SDRAM controller
186
input [1:0]              cfg_req_depth       ; // Maximum Request accepted by SDRAM controller
187
input [APP_RW-1:0]       app_req_len         ; // Application Burst Request length in 32 bit 
188 3 dinesha
input [11:0]             cfg_sdr_mode_reg    ;
189 13 dinesha
input [2:0]              cfg_sdr_cas         ; // SDRAM CAS Latency
190
input [3:0]              cfg_sdr_trcar_d     ; // Auto-refresh period
191
input [3:0]             cfg_sdr_twr_d       ; // Write recovery delay
192 3 dinesha
input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
193
input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
194
input                   app_req_dma_last;    // this signal should close the bank
195
 
196
/****************************************************************************/
197
// Internal Nets
198
 
199
// SDR_REQ_GEN
200
wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
201
wire [1:0]               r2b_ba;
202
wire [11:0]              r2b_raddr;
203
wire [11:0]              r2b_caddr;
204
wire [APP_RW-1:0]        r2b_len;
205
 
206
// SDR BANK CTL
207
wire [`SDR_REQ_ID_W-1:0]b2x_id;
208
wire [1:0]               b2x_ba;
209
wire [11:0]              b2x_addr;
210
wire [APP_RW-1:0]        b2x_len;
211
wire [1:0]               b2x_cmd;
212
 
213
// SDR_XFR_CTL
214
wire [3:0]               x2b_pre_ok;
215
wire [`SDR_REQ_ID_W-1:0]xfr_id;
216
wire [APP_DW-1:0]        app_rd_data;
217
wire                    sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n;
218
wire [SDR_BW-1:0]        sdr_dqm;
219
wire [1:0]               sdr_ba;
220
wire [11:0]              sdr_addr;
221
wire [SDR_DW-1:0]        sdr_dout;
222
wire [SDR_DW-1:0]        sdr_dout_int;
223
wire [SDR_BW-1:0]        sdr_den_n;
224
wire [SDR_BW-1:0]        sdr_den_n_int;
225
 
226
wire [1:0]               xfr_bank_sel;
227
 
228
wire [APP_AW-1:0]        app_req_addr;
229
wire [APP_RW-1:0]        app_req_len;
230
 
231
wire [APP_DW-1:0]        app_wr_data;
232 45 dinesha
wire [SDR_DW-1:0]        a2x_wrdt       ;
233 3 dinesha
wire [APP_BW-1:0]        app_wr_en_n;
234 45 dinesha
wire [SDR_BW-1:0]        a2x_wren_n;
235 3 dinesha
 
236
//wire [31:0] app_rd_data;
237 45 dinesha
wire [SDR_DW-1:0]        x2a_rddt;
238 3 dinesha
 
239
 
240
// synopsys translate_off 
241
   wire [3:0]           sdr_cmd;
242
   assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
243
// synopsys translate_on 
244
 
245 45 dinesha
assign sdr_den_n = sdr_den_n_int ;
246
assign sdr_dout  = sdr_dout_int ;
247 3 dinesha
 
248
 
249 23 dinesha
// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
250
// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
251
// register w.r.t pad sdram clk
252
reg [SDR_DW-1:0] pad_sdr_din1;
253
reg [SDR_DW-1:0] pad_sdr_din2;
254
always@(posedge pad_clk) begin
255
   pad_sdr_din1 <= pad_sdr_din;
256
end
257
 
258
always@(posedge clk) begin
259
   pad_sdr_din2 <= pad_sdr_din1;
260
end
261
 
262 45 dinesha
 
263 3 dinesha
   /****************************************************************************/
264
   // Instantiate sdr_req_gen
265
   // This module takes requests from the app, chops them to burst booundaries
266
   // if wrap=0, decodes the bank and passe the request to bank_ctl
267
 
268 9 dinesha
sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen (
269 4 dinesha
          .clk                (clk          ),
270 3 dinesha
          .reset_n            (reset_n            ),
271 13 dinesha
          .cfg_colbits        (cfg_colbits        ),
272 3 dinesha
 
273
        /* Request from app */
274
          .r2x_idle           (r2x_idle           ),
275 45 dinesha
          .req                (app_req            ),
276 3 dinesha
          .req_id             (4'b0               ),
277 45 dinesha
          .req_addr           (app_req_addr       ),
278
          .req_len            (app_req_len        ),
279 3 dinesha
          .req_wrap           (app_req_wrap       ),
280
          .req_wr_n           (app_req_wr_n       ),
281 45 dinesha
          .req_ack            (app_req_ack        ),
282 3 dinesha
          .sdr_core_busy_n    (sdr_core_busy_n    ),
283
 
284
       /* Req to bank_ctl */
285
          .r2b_req            (r2b_req            ),
286
          .r2b_req_id         (r2b_req_id         ),
287
          .r2b_start          (r2b_start          ),
288
          .r2b_last           (r2b_last           ),
289
          .r2b_wrap           (r2b_wrap           ),
290
          .r2b_ba             (r2b_ba             ),
291
          .r2b_raddr          (r2b_raddr          ),
292
          .r2b_caddr          (r2b_caddr          ),
293
          .r2b_len            (r2b_len            ),
294
          .r2b_write          (r2b_write          ),
295
          .b2r_ack            (b2r_ack            ),
296
          .b2r_arb_ok         (b2r_arb_ok         ),
297
          .sdr_width          (sdr_width          ),
298
          .sdr_init_done      (sdr_init_done      )
299
     );
300
 
301
   /****************************************************************************/
302
   // Instantiate sdr_bank_ctl
303
   // This module takes requests from sdr_req_gen, checks for page hit/miss and
304
   // issues precharge/activate commands and then passes the request to
305
   // sdr_xfr_ctl. 
306
 
307 9 dinesha
sdrc_bank_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bank_ctl (
308 4 dinesha
          .clk                (clk          ),
309 3 dinesha
          .reset_n            (reset_n            ),
310
          .a2b_req_depth      (cfg_req_depth      ),
311
 
312
      /* Req from req_gen */
313
          .r2b_req            (r2b_req            ),
314
          .r2b_req_id         (r2b_req_id         ),
315
          .r2b_start          (r2b_start          ),
316
          .r2b_last           (r2b_last           ),
317
          .r2b_wrap           (r2b_wrap           ),
318
          .r2b_ba             (r2b_ba             ),
319
          .r2b_raddr          (r2b_raddr          ),
320
          .r2b_caddr          (r2b_caddr          ),
321
          .r2b_len            (r2b_len            ),
322
          .r2b_write          (r2b_write          ),
323
          .b2r_arb_ok         (b2r_arb_ok         ),
324
          .b2r_ack            (b2r_ack            ),
325
 
326
      /* Transfer request to xfr_ctl */
327
          .b2x_idle           (b2x_idle           ),
328
          .b2x_req            (b2x_req            ),
329
          .b2x_start          (b2x_start          ),
330
          .b2x_last           (b2x_last           ),
331
          .b2x_wrap           (b2x_wrap           ),
332
          .b2x_id             (b2x_id             ),
333
          .b2x_ba             (b2x_ba             ),
334
          .b2x_addr           (b2x_addr           ),
335
          .b2x_len            (b2x_len            ),
336
          .b2x_cmd            (b2x_cmd            ),
337
          .x2b_ack            (x2b_ack            ),
338
 
339
      /* Status from xfr_ctl */
340
          .b2x_tras_ok        (b2x_tras_ok        ),
341
          .x2b_refresh        (x2b_refresh        ),
342
          .x2b_pre_ok         (x2b_pre_ok         ),
343
          .x2b_act_ok         (x2b_act_ok         ),
344
          .x2b_rdok           (x2b_rdok           ),
345
          .x2b_wrok           (x2b_wrok           ),
346
 
347
      /* for generate cuurent xfr address msb */
348 45 dinesha
          .sdr_req_norm_dma_last(app_req_dma_last),
349 3 dinesha
          .xfr_bank_sel       (xfr_bank_sel       ),
350
 
351
       /* SDRAM Timing */
352
          .tras_delay         (cfg_sdr_tras_d     ),
353
          .trp_delay          (cfg_sdr_trp_d      ),
354
          .trcd_delay         (cfg_sdr_trcd_d     )
355
      );
356
 
357
   /****************************************************************************/
358
   // Instantiate sdr_xfr_ctl
359
   // This module takes requests from sdr_bank_ctl, runs the transfer and
360
   // controls data flow to/from the app. At the end of the transfer it issues a
361
   // burst terminate if not at the end of a burst and another command to this
362
   // bank is not available.
363
 
364 9 dinesha
sdrc_xfr_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_xfr_ctl (
365 4 dinesha
          .clk                (clk          ),
366 3 dinesha
          .reset_n            (reset_n            ),
367
 
368
      /* Transfer request from bank_ctl */
369
          .r2x_idle           (r2x_idle           ),
370
          .b2x_idle           (b2x_idle           ),
371
          .b2x_req            (b2x_req            ),
372
          .b2x_start          (b2x_start          ),
373
          .b2x_last           (b2x_last           ),
374
          .b2x_wrap           (b2x_wrap           ),
375
          .b2x_id             (b2x_id             ),
376
          .b2x_ba             (b2x_ba             ),
377
          .b2x_addr           (b2x_addr           ),
378
          .b2x_len            (b2x_len            ),
379
          .b2x_cmd            (b2x_cmd            ),
380
          .x2b_ack            (x2b_ack            ),
381
 
382
       /* Status to bank_ctl, req_gen */
383
          .b2x_tras_ok        (b2x_tras_ok        ),
384
          .x2b_refresh        (x2b_refresh        ),
385
          .x2b_pre_ok         (x2b_pre_ok         ),
386
          .x2b_act_ok         (x2b_act_ok         ),
387
          .x2b_rdok           (x2b_rdok           ),
388
          .x2b_wrok           (x2b_wrok           ),
389
 
390
       /* SDRAM I/O */
391
          .sdr_cs_n           (sdr_cs_n           ),
392
          .sdr_cke            (sdr_cke            ),
393
          .sdr_ras_n          (sdr_ras_n          ),
394
          .sdr_cas_n          (sdr_cas_n          ),
395
          .sdr_we_n           (sdr_we_n           ),
396
          .sdr_dqm            (sdr_dqm            ),
397
          .sdr_ba             (sdr_ba             ),
398
          .sdr_addr           (sdr_addr           ),
399 23 dinesha
          .sdr_din            (pad_sdr_din2       ),
400 3 dinesha
          .sdr_dout           (sdr_dout_int       ),
401
          .sdr_den_n          (sdr_den_n_int      ),
402
      /* Data Flow to the app */
403 45 dinesha
          .x2a_rdstart        (x2a_rdstart        ),
404
          .x2a_wrstart        (x2a_wrstart        ),
405 3 dinesha
          .x2a_id             (xfr_id             ),
406 44 dinesha
          .x2a_rdlast         (x2a_rdlast         ),
407 45 dinesha
          .x2a_wrlast         (x2a_wrlast         ),
408
          .a2x_wrdt           (a2x_wrdt           ),
409
          .a2x_wren_n         (a2x_wren_n         ),
410
          .x2a_wrnext         (x2a_wrnext         ),
411
          .x2a_rddt           (x2a_rddt           ),
412
          .x2a_rdok           (x2a_rdok           ),
413 3 dinesha
          .sdr_init_done      (sdr_init_done      ),
414
 
415
      /* SDRAM Parameters */
416
          .sdram_enable       (cfg_sdr_en         ),
417
          .sdram_mode_reg     (cfg_sdr_mode_reg   ),
418
 
419
      /* current xfr bank */
420
          .xfr_bank_sel       (xfr_bank_sel       ),
421
 
422
      /* SDRAM Timing */
423
          .cas_latency        (cfg_sdr_cas        ),
424
          .trp_delay          (cfg_sdr_trp_d      ),
425
          .trcar_delay        (cfg_sdr_trcar_d    ),
426
          .twr_delay          (cfg_sdr_twr_d      ),
427
          .rfsh_time          (cfg_sdr_rfsh       ),
428
          .rfsh_rmax          (cfg_sdr_rfmax      )
429
    );
430
 
431 33 dinesha
   /****************************************************************************/
432
   // Instantiate sdr_bs_convert
433
   //    This model handle the bus with transaltion from application layer to
434
   //       8/16/32 SDRAM Memory format
435
   //     During Write Phase, this block split the data as per SDRAM Width
436
   //     During Read Phase, This block does the re-packing based on SDRAM
437
   //     Width
438
   //---------------------------------------------------------------------------
439 9 dinesha
sdrc_bs_convert #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bs_convert (
440 4 dinesha
          .clk                (clk          ),
441 3 dinesha
          .reset_n            (reset_n            ),
442
          .sdr_width          (sdr_width          ),
443
 
444 44 dinesha
   /* Control Signal from xfr ctrl */
445 45 dinesha
          // Read Interface Inputs
446
          .x2a_rdstart        (x2a_rdstart        ),
447 44 dinesha
          .x2a_rdlast         (x2a_rdlast         ),
448 45 dinesha
          .x2a_rdok           (x2a_rdok           ),
449
          // Read Interface outputs
450
          .x2a_rddt           (x2a_rddt           ),
451 44 dinesha
 
452 45 dinesha
          // Write Interface, Inputs
453
          .x2a_wrstart        (x2a_wrstart        ),
454
          .x2a_wrlast         (x2a_wrlast         ),
455
          .x2a_wrnext         (x2a_wrnext         ),
456 44 dinesha
 
457 45 dinesha
          // Write Interface, Outputs
458
          .a2x_wrdt           (a2x_wrdt           ),
459
          .a2x_wren_n         (a2x_wren_n         ),
460 44 dinesha
 
461 45 dinesha
   /* Control Signal from sdrc_bank_ctl  */
462
 
463 44 dinesha
   /*  Control Signal from/to to application i/f  */
464 3 dinesha
          .app_wr_data        (app_wr_data        ),
465
          .app_wr_en_n        (app_wr_en_n        ),
466
          .app_wr_next        (app_wr_next_req    ),
467 45 dinesha
          .app_last_wr        (app_last_wr        ),
468 3 dinesha
          .app_rd_data        (app_rd_data        ),
469 45 dinesha
          .app_rd_valid       (app_rd_valid       ),
470
          .app_last_rd        (app_last_rd        )
471 44 dinesha
 
472 3 dinesha
       );
473
 
474
endmodule // sdrc_core

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