OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [lib/] [sync_fifo.v] - Blame information for rev 31

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 31 dinesha
/*********************************************************************
2
 
3
  This file is part of the sdram controller project
4
  http://www.opencores.org/cores/sdr_ctrl/
5
 
6
  Description: SYNC FIFO
7
  Parameters:
8
      W : Width (integer)
9
      D : Depth (integer, power of 2, 4 to 256)
10
 
11
  To Do:
12
    nothing
13
 
14
  Author(s):  Dinesh Annayya, dinesha@opencores.org
15
 
16
 Copyright (C) 2000 Authors and OPENCORES.ORG
17
 
18
 This source file may be used and distributed without
19
 restriction provided that this copyright statement is not
20
 removed from the file and that any derivative work contains
21
 the original copyright notice and the associated disclaimer.
22
 
23
 This source file is free software; you can redistribute it
24
 and/or modify it under the terms of the GNU Lesser General
25
 Public License as published by the Free Software Foundation;
26
 either version 2.1 of the License, or (at your option) any
27
later version.
28
 
29
 This source is distributed in the hope that it will be
30
 useful, but WITHOUT ANY WARRANTY; without even the implied
31
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
32
 PURPOSE.  See the GNU Lesser General Public License for more
33
 details.
34
 
35
 You should have received a copy of the GNU Lesser General
36
 Public License along with this source; if not, download it
37
 from http://www.opencores.org/lgpl.shtml
38
 
39
*******************************************************************/
40
 
41
 
42
module sync_fifo (clk,
43
                  reset_n,
44
                  wr_en,
45
                  wr_data,
46
                  full,
47
                  empty,
48
                  rd_en,
49
                  rd_data);
50
 
51
   parameter W = 8;
52
   parameter D = 4;
53
 
54
   parameter AW = (D == 4)   ? 2 :
55
                  (D == 8)   ? 3 :
56
                  (D == 16)  ? 4 :
57
                  (D == 32)  ? 5 :
58
                  (D == 64)  ? 6 :
59
                  (D == 128) ? 7 :
60
                  (D == 256) ? 8 : 0;
61
 
62
   output [W-1 : 0]  rd_data;
63
   input [W-1 : 0]   wr_data;
64
   input             clk, reset_n, wr_en, rd_en;
65
   output            full, empty;
66
 
67
   // synopsys translate_off
68
 
69
   initial begin
70
      if (AW == 0) begin
71
         $display ("%m : ERROR!!! Fifo depth %d not in range 4 to 256", D);
72
      end // if (AW == 0)
73
   end // initial begin
74
 
75
   // synopsys translate_on
76
 
77
 
78
   reg [W-1 : 0]    mem[D-1 : 0];
79
   reg [AW-1 : 0]   rd_ptr, wr_ptr;
80
   reg              full, empty;
81
 
82
   wire [W-1 : 0]   rd_data;
83
 
84
   always @ (posedge clk or negedge reset_n)
85
      if (reset_n == 1'b0) begin
86
         wr_ptr <= {AW{1'b0}} ;
87
      end
88
      else begin
89
         if (wr_en & !full) begin
90
            wr_ptr <= wr_ptr + 1'b1 ;
91
         end
92
      end
93
 
94
   always @ (posedge clk or negedge reset_n)
95
      if (reset_n == 1'b0) begin
96
         rd_ptr <= {AW{1'b0}} ;
97
      end
98
      else begin
99
         if (rd_en & !empty) begin
100
            rd_ptr <= rd_ptr + 1'b1 ;
101
         end
102
      end
103
 
104
 
105
   always @ (posedge clk or negedge reset_n)
106
      if (reset_n == 1'b0) begin
107
         empty <= 1'b1 ;
108
      end
109
      else begin
110
         empty <= (((wr_ptr - rd_ptr) == {{(AW-1){1'b0}}, 1'b1}) & rd_en & ~wr_en) ? 1'b1 :
111
                   ((wr_ptr == rd_ptr) & ~rd_en & wr_en) ? 1'b0 : empty ;
112
      end
113
 
114
   always @ (posedge clk or negedge reset_n)
115
      if (reset_n == 1'b0) begin
116
         full <= 1'b0 ;
117
      end
118
      else begin
119
         full <= (((wr_ptr - rd_ptr) == {{(AW-1){1'b1}}, 1'b0}) & ~rd_en & wr_en) ? 1'b1 :
120
                 (((wr_ptr - rd_ptr) == {AW{1'b1}}) & rd_en & ~wr_en) ? 1'b0 : full ;
121
      end
122
 
123
   always @ (posedge clk)
124
      if (wr_en)
125
         mem[wr_ptr] <= wr_data;
126
 
127
assign  rd_data = mem[rd_ptr];
128
 
129
 
130
// synopsys translate_off
131
   always @(posedge clk) begin
132
      if (wr_en && full) begin
133
         $display("%m : Error! sfifo overflow!");
134
      end
135
   end
136
 
137
   always @(posedge clk) begin
138
      if (rd_en && empty) begin
139
         $display("%m : error! sfifo underflow!");
140
      end
141
   end
142
 
143
// synopsys translate_on
144
//---------------------------------------
145
 
146
endmodule
147
 
148
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.