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[/] [sdr_ctrl/] [trunk/] [rtl/] [wb2sdrc/] [wb2sdrc.v] - Blame information for rev 31

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1 31 dinesha
/*********************************************************************
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  This file is part of the sdram controller project
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  http://www.opencores.org/cores/sdr_ctrl/
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  Description: WISHBONE to SDRAM Controller Bus Transalator
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  This module translate the WISHBONE protocol to custom sdram controller i/f
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  To Do:
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    nothing
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  Author(s):  Dinesh Annayya, dinesha@opencores.org
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 Copyright (C) 2000 Authors and OPENCORES.ORG
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 This source file may be used and distributed without
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 restriction provided that this copyright statement is not
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 removed from the file and that any derivative work contains
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 the original copyright notice and the associated disclaimer.
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 This source file is free software; you can redistribute it
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 and/or modify it under the terms of the GNU Lesser General
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 Public License as published by the Free Software Foundation;
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 either version 2.1 of the License, or (at your option) any
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later version.
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 This source is distributed in the hope that it will be
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 useful, but WITHOUT ANY WARRANTY; without even the implied
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 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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 PURPOSE.  See the GNU Lesser General Public License for more
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 details.
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 You should have received a copy of the GNU Lesser General
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 Public License along with this source; if not, download it
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 from http://www.opencores.org/lgpl.shtml
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*******************************************************************/
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module wb2sdrc (
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      // WB bus
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      wb_rst_i           ,
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      wb_clk_i           ,
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      wb_stb_i           ,
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      wb_ack_o           ,
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      wb_addr_i          ,
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      wb_we_i            ,
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      wb_dat_i           ,
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      wb_sel_i           ,
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      wb_dat_o           ,
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      wb_cyc_i           ,
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      wb_cti_i           ,
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      //SDRAM Controller Hand-Shake Signal 
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      sdram_clk          ,
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      sdram_resetn       ,
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      sdr_req            ,
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      sdr_req_addr       ,
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      sdr_req_len        ,
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      sdr_req_wr_n       ,
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      sdr_req_ack        ,
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      sdr_busy_n         ,
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      sdr_wr_en_n        ,
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      sdr_wr_next        ,
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      sdr_rd_valid       ,
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      sdr_last_rd        ,
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      sdr_wr_data        ,
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      sdr_rd_data
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      );
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parameter      dw              = 32;  // data width
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parameter      tw              = 8;   // tag id width
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parameter      bl              = 9;   // burst_lenght_width 
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//--------------------------------------
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// Wish Bone Interface
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// -------------------------------------      
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input           wb_rst_i           ;
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input           wb_clk_i           ;
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input           wb_stb_i           ;
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output          wb_ack_o           ;
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input [29:0]    wb_addr_i          ;
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input           wb_we_i            ; // 1 - Write, 0 - Read
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input [dw-1:0]  wb_dat_i           ;
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input [dw/8-1:0]wb_sel_i           ; // Byte enable
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output [dw-1:0] wb_dat_o           ;
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input           wb_cyc_i           ;
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input  [2:0]    wb_cti_i           ;
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/***************************************************
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The Cycle Type Idenfier [CTI_IO()] Address Tag provides
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additional information about the current cycle.
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The MASTER sends this information to the SLAVE. The SLAVE can use this
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information to prepare the response for the next cycle.
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Table 4-2 Cycle Type Identifiers
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CTI_O(2:0) Description
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000 Classic cycle.
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001 Constant address burst cycle
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010 Incrementing burst cycle
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011 Reserved
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100 Reserved
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101 Reserved
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110 Reserved
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111 End-of-Burst
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****************************************************/
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//--------------------------------------------
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// SDRAM controller Interface 
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//--------------------------------------------
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input                   sdram_clk           ; // sdram clock
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input                   sdram_resetn        ; // sdram reset
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output                  sdr_req            ; // SDRAM request
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output [29:0]           sdr_req_addr       ; // SDRAM Request Address
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output [bl-1:0]         sdr_req_len        ;
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output                  sdr_req_wr_n       ; // 0 - Write, 1 -> Read
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input                   sdr_req_ack        ; // SDRAM request Accepted
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input                   sdr_busy_n         ; // 0 -> sdr busy
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output [dw/8-1:0]       sdr_wr_en_n        ; // Active low sdr byte-wise write data valid
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input                   sdr_wr_next        ; // Ready to accept the next write
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input                   sdr_rd_valid       ; // sdr read valid
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input                   sdr_last_rd        ; // Indicate last Read of Burst Transfer
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output [dw-1:0]         sdr_wr_data        ; // sdr write data
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input  [dw-1:0]         sdr_rd_data        ; // sdr read data
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//----------------------------------------------------
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// Wire Decleration
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// ---------------------------------------------------
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wire                    cmdfifo_full;
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wire                    cmdfifo_empty;
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wire                    wrdatafifo_full;
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wire                    wrdatafifo_empty;
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wire                    tagfifo_full;
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wire                    tagfifo_empty;
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wire                    rddatafifo_empty;
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wire                    rddatafifo_full;
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reg                     pending_read;
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// Generate Address Enable only when internal fifo (Address + data are not full
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assign wb_ack_o = (wb_stb_i && wb_cyc_i && wb_we_i) ?  // Write Phase
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                          ((!cmdfifo_full) && (!wrdatafifo_full)) :
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                  (wb_stb_i && wb_cyc_i && !wb_we_i) ? // Read Phase 
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                           !rddatafifo_empty : 1'b0;
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// Accept the cmdfifo only when burst start + address enable + address
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// valid is asserted
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wire           cmdfifo_wr   = (wb_stb_i && wb_cyc_i && wb_we_i) ? wb_ack_o :
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                              (wb_stb_i && wb_cyc_i && !wb_we_i) ? !pending_read: 1'b0 ;
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wire           cmdfifo_rd   = sdr_req_ack;
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assign         sdr_req      = !cmdfifo_empty;
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wire [bl-1:0]  burst_length  = 1;  // 0 Mean 1 Transfer
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always @(posedge wb_rst_i or posedge wb_clk_i) begin
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   if(wb_rst_i) begin
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       pending_read <= 1'b0;
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   end else begin
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      pending_read <=  wb_stb_i & wb_cyc_i & !wb_we_i & !wb_ack_o;
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   end
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end
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   // Address + Burst Length + W/R Request 
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    async_fifo #(.W(30+bl+1),.DP(4)) u_cmdfifo (
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     // Write Path Sys CLock Domain
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          .wr_clk     (wb_clk_i),
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          .wr_reset_n (!wb_rst_i),
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          .wr_en      (cmdfifo_wr),
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          .wr_data    ({burst_length,
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                        !wb_we_i,
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                       wb_addr_i}),
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          .afull      (),
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          .full       (cmdfifo_full),
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     // Read Path, SDRAM clock domain
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          .rd_clk     (sdram_clk),
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          .rd_reset_n (sdram_resetn),
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          .aempty     (),
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          .empty      (cmdfifo_empty),
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          .rd_en      (cmdfifo_rd),
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          .rd_data    ({sdr_req_len,
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                     sdr_req_wr_n,
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                     sdr_req_addr})
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     );
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// synopsys translate_off
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always @(posedge wb_clk_i) begin
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  if (cmdfifo_full == 1'b1 && cmdfifo_wr == 1'b1)  begin
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     $display("ERROR:%m COMMAND FIFO WRITE OVERFLOW");
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  end
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end
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// synopsys translate_off
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always @(posedge sdram_clk) begin
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   if (cmdfifo_empty == 1'b1 && cmdfifo_rd == 1'b1) begin
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      $display("ERROR:%m COMMAND FIFO READ OVERFLOW");
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   end
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end
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// synopsys translate_on
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wire  wrdatafifo_wr  = wb_ack_o & wb_we_i ;
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wire  wrdatafifo_rd  = sdr_wr_next;
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   // Write DATA + Data Mask FIFO
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    async_fifo #(.W(dw+(dw/8)), .DP(16)) u_wrdatafifo (
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       // Write Path , System clock domain
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          .wr_clk     (wb_clk_i),
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          .wr_reset_n (!wb_rst_i),
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          .wr_en   (wrdatafifo_wr),
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          .wr_data ({~wb_sel_i,
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                     wb_dat_i}),
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          .afull    (),
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          .full     (wrdatafifo_full),
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       // Read Path , SDRAM clock domain
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          .rd_clk     (sdram_clk),
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          .rd_reset_n (sdram_resetn),
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          .aempty     (),
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          .empty      (wrdatafifo_empty),
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          .rd_en      (wrdatafifo_rd),
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          .rd_data    ({sdr_wr_en_n,
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                        sdr_wr_data})
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     );
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// synopsys translate_off
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always @(posedge wb_clk_i) begin
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  if (wrdatafifo_full == 1'b1 && wrdatafifo_wr == 1'b1)  begin
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     $display("ERROR:%m WRITE DATA FIFO WRITE OVERFLOW");
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  end
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end
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always @(posedge sdram_clk) begin
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   if (wrdatafifo_empty == 1'b1 && wrdatafifo_rd == 1'b1) begin
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      $display("ERROR:%m WRITE DATA FIFO READ OVERFLOW");
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   end
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end
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// synopsys translate_on
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// -------------------------------------------------------------------
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//  READ DATA FIFO
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//  ------------------------------------------------------------------
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wire    rd_eop; // last read indication
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wire    rddatafifo_wr = sdr_rd_valid;
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wire    rddatafifo_rd = wb_ack_o & !wb_we_i & (rddatafifo_empty == 0);
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   // READ DATA FIFO depth is kept small, assuming that Sys-CLock > SDRAM Clock
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   // READ DATA + EOP
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    async_fifo #(.W(dw+1), .DP(4)) u_rddatafifo (
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       // Write Path , SDRAM clock domain
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          .wr_clk     (sdram_clk),
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          .wr_reset_n (sdram_resetn),
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          .wr_en      (rddatafifo_wr),
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          .wr_data    ({sdr_last_rd,
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                        sdr_rd_data}),
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          .afull      (),
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          .full       (rddatafifo_full),
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       // Read Path , SYS clock domain
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          .rd_clk     (wb_clk_i),
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          .rd_reset_n (!wb_rst_i),
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          .empty      (rddatafifo_empty),
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          .aempty     (),
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          .rd_en      (rddatafifo_rd),
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          .rd_data    ({rd_eop,
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                        wb_dat_o})
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     );
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// synopsys translate_off
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always @(posedge sdram_clk) begin
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  if (rddatafifo_full == 1'b1 && rddatafifo_wr == 1'b1)  begin
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     $display("ERROR:%m READ DATA FIFO WRITE OVERFLOW");
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  end
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end
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always @(posedge wb_clk_i) begin
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   if (rddatafifo_empty == 1'b1 && rddatafifo_rd == 1'b1) begin
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      $display("ERROR:%m READ DATA FIFO READ OVERFLOW");
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   end
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end
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// synopsys translate_on
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endmodule

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