URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [read.me] - Blame information for rev 5

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1. To run SDRM 16 Bit Test
   run_modelsim SDR_16BITa
   Note: All the logs will be prefixed with SDR_16BBIT
2. To run SDRAM 32 Bit Test
   run_modelsim SDR_32BIT
   Note: All the logs will be prefixed with SDR_32BBIT
3. to debug the test in modelsim
   ./compile_modelsim 
   vsim tb_top &
 

Line No.	Rev	Author	Line
1	5	dinesha	`1. To run SDRM 16 Bit Test`
2			`run_modelsim SDR_16BITa`
3			`Note: All the logs will be prefixed with SDR_16BBIT`
4			`2. To run SDRAM 32 Bit Test`
5			`run_modelsim SDR_32BIT`
6			`Note: All the logs will be prefixed with SDR_32BBIT`
7			`3. to debug the test in modelsim`
8			`./compile_modelsim`
9			`vsim tb_top &`
10

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Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [read.me] - Blame information for rev 5