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1 8 dinesha
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////                                                              ////
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////  This file is part of the SDRAM Controller project           ////
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////  http://www.opencores.org/cores/sdr_ctrl/                    ////
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////                                                              ////
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////  Description                                                 ////
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////  SDRAM CTRL definitions.                                     ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43
 
44
`timescale 1ns/1ps
45
 
46 24 dinesha
// This testbench verify with SDRAM TOP
47
 
48 8 dinesha
module tb_top;
49
 
50 30 dinesha
parameter P_SYS  = 10;     //    200MHz
51
parameter P_SDR  = 20;     //    100MHz
52 8 dinesha
 
53
// General
54
reg            RESETN;
55
reg            sdram_clk;
56 30 dinesha
reg            sys_clk;
57 8 dinesha
 
58 30 dinesha
initial sys_clk = 0;
59 8 dinesha
initial sdram_clk = 0;
60
 
61 30 dinesha
always #(P_SYS/2) sys_clk = !sys_clk;
62
always #(P_SDR/2) sdram_clk = !sdram_clk;
63 8 dinesha
 
64
parameter      dw              = 32;  // data width
65
parameter      tw              = 8;   // tag id width
66
parameter      bl              = 5;   // burst_lenght_width
67
 
68
//-------------------------------------------
69 30 dinesha
// WISH BONE Interface
70 8 dinesha
//-------------------------------------------
71 30 dinesha
//--------------------------------------
72
// Wish Bone Interface
73
// -------------------------------------
74
reg             wb_stb_i           ;
75
wire            wb_ack_o           ;
76
reg  [29:0]     wb_addr_i          ;
77
reg             wb_we_i            ; // 1 - Write, 0 - Read
78
reg  [dw-1:0]   wb_dat_i           ;
79
reg  [dw/8-1:0] wb_sel_i           ; // Byte enable
80
wire  [dw-1:0]  wb_dat_o           ;
81
reg             wb_cyc_i           ;
82
reg   [2:0]     wb_cti_i           ;
83 8 dinesha
 
84 30 dinesha
 
85
 
86 8 dinesha
//--------------------------------------------
87
// SDRAM I/F
88
//--------------------------------------------
89
 
90
`ifdef SDR_32BIT
91
   wire [31:0]           Dq                 ; // SDRAM Read/Write Data Bus
92
   wire [31:0]           sdr_dout           ; // SDRAM Data Out
93
   wire [31:0]           pad_sdr_din        ; // SDRAM Data Input
94
   wire [3:0]            sdr_den_n          ; // SDRAM Data Enable
95
   wire [3:0]            sdr_dqm            ; // SDRAM DATA Mask
96 18 dinesha
`elsif SDR_16BIT
97 8 dinesha
   wire [15:0]           Dq                 ; // SDRAM Read/Write Data Bus
98
   wire [15:0]           sdr_dout           ; // SDRAM Data Out
99
   wire [15:0]           pad_sdr_din        ; // SDRAM Data Input
100
   wire [1:0]            sdr_den_n          ; // SDRAM Data Enable
101
   wire [1:0]            sdr_dqm            ; // SDRAM DATA Mask
102 18 dinesha
`else
103
   wire [7:0]           Dq                 ; // SDRAM Read/Write Data Bus
104
   wire [7:0]           sdr_dout           ; // SDRAM Data Out
105
   wire [7:0]           pad_sdr_din        ; // SDRAM Data Input
106
   wire [0:0]           sdr_den_n          ; // SDRAM Data Enable
107
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
108 8 dinesha
`endif
109
 
110
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
111
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
112
wire                  sdr_init_done      ; // SDRAM Init Done
113
 
114
// to fix the sdram interface timing issue
115 30 dinesha
wire #(2.0) sdram_clk_d   = sdram_clk;
116
wire #(1.0) sdram_pad_clk = sdram_clk_d;
117 8 dinesha
 
118
`ifdef SDR_32BIT
119
 
120 30 dinesha
   sdrc_top #(.SDR_DW(32),.SDR_BW(4)) u_dut(
121 18 dinesha
`elsif SDR_16BIT
122 30 dinesha
   sdrc_top #(.SDR_DW(16),.SDR_BW(2)) u_dut(
123 18 dinesha
`else  // 8 BIT SDRAM
124 30 dinesha
   sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
125 8 dinesha
`endif
126
      // System
127
`ifdef SDR_32BIT
128 18 dinesha
          .sdr_width          (2'b00              ), // 32 BIT SDRAM
129
`elsif SDR_16BIT
130
          .sdr_width          (2'b01              ), // 16 BIT SDRAM
131
`else
132
          .sdr_width          (2'b10              ), // 8 BIT SDRAM
133 8 dinesha
`endif
134 12 dinesha
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
135 8 dinesha
 
136 30 dinesha
/* WISH BONE */
137
          .wb_rst_i           (!RESETN            ),
138
          .wb_clk_i           (sys_clk            ),
139 8 dinesha
 
140 30 dinesha
          .wb_stb_i           (wb_stb_i           ),
141
          .wb_ack_o           (wb_ack_o           ),
142
          .wb_addr_i          (wb_addr_i          ),
143
          .wb_we_i            (wb_we_i            ),
144
          .wb_dat_i           (wb_dat_i           ),
145
          .wb_sel_i           (wb_sel_i           ),
146
          .wb_dat_o           (wb_dat_o           ),
147
          .wb_cyc_i           (wb_cyc_i           ),
148
          .wb_cti_i           (wb_cti_i           ),
149 8 dinesha
 
150
/* Interface to SDRAMs */
151 30 dinesha
          .sdram_clk          (sdram_clk          ),
152
          .sdram_pad_clk      (sdram_pad_clk      ),
153
          .sdram_resetn       (RESETN             ),
154 8 dinesha
          .sdr_cs_n           (sdr_cs_n           ),
155
          .sdr_cke            (sdr_cke            ),
156
          .sdr_ras_n          (sdr_ras_n          ),
157
          .sdr_cas_n          (sdr_cas_n          ),
158
          .sdr_we_n           (sdr_we_n           ),
159
          .sdr_dqm            (sdr_dqm            ),
160
          .sdr_ba             (sdr_ba             ),
161
          .sdr_addr           (sdr_addr           ),
162
          .pad_sdr_din        (Dq                 ),
163
          .sdr_dout           (sdr_dout           ),
164
          .sdr_den_n          (sdr_den_n          ),
165
 
166
    /* Parameters */
167
          .sdr_init_done      (sdr_init_done      ),
168
          .cfg_req_depth      (2'h2               ),            //how many req. buffer should hold
169
          .cfg_sdr_en         (1'b1               ),
170
          .cfg_sdr_mode_reg   (12'h033            ),
171
          .cfg_sdr_tras_d     (4'h4               ),
172
          .cfg_sdr_trp_d      (4'h2               ),
173
          .cfg_sdr_trcd_d     (4'h2               ),
174 22 dinesha
          .cfg_sdr_cas        (3'h3               ),
175 8 dinesha
          .cfg_sdr_trcar_d    (4'h7               ),
176
          .cfg_sdr_twr_d      (4'h1               ),
177
          .cfg_sdr_rfsh       (12'hC35            ),
178
          .cfg_sdr_rfmax      (3'h6               )
179
 
180
);
181
 
182
 
183
`ifdef SDR_32BIT
184
  assign Dq[7:0]    = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]   : 8'hZZ;
185
  assign Dq[15:8]   = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8]  : 8'hZZ;
186
  assign Dq[23:16]  = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
187
  assign Dq[31:24]  = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
188
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
189
          .Dq                 (Dq                 ) ,
190
          .Addr               (sdr_addr           ),
191
          .Ba                 (sdr_ba             ),
192 22 dinesha
          .Clk                (sdram_clk_d        ),
193 8 dinesha
          .Cke                (sdr_cke            ),
194
          .Cs_n               (sdr_cs_n           ),
195
          .Ras_n              (sdr_ras_n          ),
196
          .Cas_n              (sdr_cas_n          ),
197
          .We_n               (sdr_we_n           ),
198
          .Dqm                (sdr_dqm            )
199
     );
200
 
201 18 dinesha
`elsif SDR_16BIT
202 8 dinesha
 
203
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
204
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
205
 
206
   IS42VM16400K u_sdram16 (
207
          .dq                 (Dq                 ),
208
          .addr               (sdr_addr           ),
209
          .ba                 (sdr_ba             ),
210 22 dinesha
          .clk                (sdram_clk_d        ),
211 8 dinesha
          .cke                (sdr_cke            ),
212
          .csb                (sdr_cs_n           ),
213
          .rasb               (sdr_ras_n          ),
214
          .casb               (sdr_cas_n          ),
215
          .web                (sdr_we_n           ),
216
          .dqm                (sdr_dqm            )
217
    );
218 18 dinesha
`else
219
 
220
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
221
 
222
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
223
          .Dq                 (Dq                 ) ,
224
          .Addr               (sdr_addr           ),
225
          .Ba                 (sdr_ba             ),
226 22 dinesha
          .Clk                (sdram_clk_d        ),
227 18 dinesha
          .Cke                (sdr_cke            ),
228
          .Cs_n               (sdr_cs_n           ),
229
          .Ras_n              (sdr_ras_n          ),
230
          .Cas_n              (sdr_cas_n          ),
231
          .We_n               (sdr_we_n           ),
232
          .Dqm                (sdr_dqm            )
233
     );
234 8 dinesha
`endif
235
 
236
//--------------------
237
// Write/Read Burst FIFO
238
//--------------------
239
int wrdfifo[$]; // write data fifo
240
int rddfifo[$]; // read data fifo
241
 
242
reg [31:0] read_data;
243
reg [31:0] ErrCnt;
244
int k;
245
reg [31:0] StartAddr;
246
/////////////////////////////////////////////////////////////////////////
247
// Test Case
248
/////////////////////////////////////////////////////////////////////////
249
 
250
initial begin //{
251
  ErrCnt          = 0;
252 30 dinesha
   wb_addr_i      = 0;
253
   wb_dat_i      = 0;
254
   wb_sel_i       = 4'h0;
255
   wb_we_i        = 0;
256
   wb_stb_i       = 0;
257
   wb_cyc_i       = 0;
258 8 dinesha
 
259
  RESETN    = 1'h1;
260
 
261
 #100
262
  // Applying reset
263
  RESETN    = 1'h0;
264
  #10000;
265
  // Releasing reset
266
  RESETN    = 1'h1;
267
  #1000;
268
  wait(u_dut.sdr_init_done == 1);
269
 
270
  #1000;
271
 
272
  wrdfifo.push_back(32'h11223344);
273
  wrdfifo.push_back(32'h22334455);
274
  wrdfifo.push_back(32'h33445566);
275
  wrdfifo.push_back(32'h44556677);
276
  wrdfifo.push_back(32'h55667788);
277
 
278
  burst_write(32'h40000);
279
 #1000;
280
  burst_read(32'h40000);
281
 
282
 #1000;
283
  burst_write(32'h7000_0000);
284
 #1000;
285
  burst_read(32'h7000_0000);
286
 
287
  for(k=0; k < 20; k++) begin
288
     StartAddr = $random & 32'h07FFFFFF;
289
     burst_write(StartAddr);
290
    #1000;
291
     burst_read(StartAddr);
292
  end
293
 
294
 
295
  #10000;
296
 
297
        $display("###############################");
298
    if(ErrCnt == 0)
299
        $display("STATUS: SDRAM Write/Read TEST PASSED");
300
    else
301
        $display("ERROR:  SDRAM Write/Read TEST FAILED");
302
        $display("###############################");
303
 
304
    $finish;
305
end
306
 
307
task burst_write;
308
input [31:0] Address;
309
int i;
310
begin
311 30 dinesha
   @ (negedge sys_clk);
312 8 dinesha
   $display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
313
 
314
   for(i=0; i < wrdfifo.size; i++) begin
315 30 dinesha
      wb_stb_i        = 1;
316
      wb_cyc_i        = 1;
317
      wb_we_i         = 1;
318
      wb_sel_i        = 4'b1111;
319
      wb_addr_i       = Address[31:2]+i;
320
      wb_dat_i        = wrdfifo[i];
321 8 dinesha
 
322
      do begin
323 30 dinesha
          @ (posedge sys_clk);
324
      end while(wb_ack_o == 1'b0);
325
          @ (negedge sys_clk);
326 8 dinesha
 
327 30 dinesha
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,wb_addr_i,wb_dat_i);
328 8 dinesha
   end
329 30 dinesha
   wb_stb_i           = 0;
330
   wb_cyc_i           = 0;
331 8 dinesha
end
332
endtask
333
 
334
task burst_read;
335
input [31:0] Address;
336
 
337
int i,j;
338
reg [31:0]   rd_data;
339
begin
340 30 dinesha
   @ (negedge sys_clk);
341 8 dinesha
 
342 30 dinesha
      for(j=0; j < wrdfifo.size; j++) begin
343
         wb_stb_i        = 1;
344
         wb_cyc_i        = 1;
345
         wb_we_i         = 0;
346
         wb_addr_i       = Address[31:2]+j;
347 8 dinesha
 
348 30 dinesha
         do begin
349
             @ (posedge sys_clk);
350
         end while(wb_ack_o == 1'b0);
351
         if(wb_dat_o !== wrdfifo[j]) begin
352
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,wb_addr_i,wb_dat_o,wrdfifo[j]);
353 8 dinesha
             ErrCnt = ErrCnt+1;
354
         end else begin
355 30 dinesha
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,wb_addr_i,wb_dat_o);
356 8 dinesha
         end
357
         @ (negedge sdram_clk);
358
      end
359 30 dinesha
   wb_stb_i           = 0;
360
   wb_cyc_i           = 0;
361 8 dinesha
end
362
endtask
363
 
364
 
365
endmodule

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