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[/] [sdram_16bit/] [trunk/] [rtl/] [sdram.v] - Blame information for rev 2

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1 2 ultra_embe
//-----------------------------------------------------------------
2
//                      Simple SDRAM Controller
3
//                              V0.1
4
//                        Ultra-Embedded.com
5
//                          Copyright 2015
6
//
7
//                 Email: admin@ultra-embedded.com
8
//
9
//                         License: GPL
10
// If you would like a version with a more permissive license for
11
// use in closed source commercial applications please contact me
12
// for details.
13
//-----------------------------------------------------------------
14
//
15
// This file is open source HDL; you can redistribute it and/or 
16
// modify it under the terms of the GNU General Public License as 
17
// published by the Free Software Foundation; either version 2 of 
18
// the License, or (at your option) any later version.
19
//
20
// This file is distributed in the hope that it will be useful,
21
// but WITHOUT ANY WARRANTY; without even the implied warranty of
22
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23
// GNU General Public License for more details.
24
//
25
// You should have received a copy of the GNU General Public 
26
// License along with this file; if not, write to the Free Software
27
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28
// USA
29
//-----------------------------------------------------------------
30
module sdram
31
 
32
//-----------------------------------------------------------------
33
// Params
34
//-----------------------------------------------------------------
35
#(
36
    parameter    SDRAM_MHZ             = 50,
37
    parameter    SDRAM_ADDR_W          = 24,
38
    parameter    SDRAM_COL_W           = 9,
39
    parameter    SDRAM_BANK_W          = 2,
40
    parameter    SDRAM_DQM_W           = 2,
41
    parameter    SDRAM_BANKS           = 2 ** SDRAM_BANK_W,
42
    parameter    SDRAM_ROW_W           = SDRAM_ADDR_W - SDRAM_COL_W - SDRAM_BANK_W,
43
    parameter    SDRAM_REFRESH_CNT     = 2 ** SDRAM_ROW_W,
44
    parameter    SDRAM_START_DELAY     = 100000 / (1000 / SDRAM_MHZ), // 100uS
45
    parameter    SDRAM_REFRESH_CYCLES  = (64000*SDRAM_MHZ) / SDRAM_REFRESH_CNT-1,
46
    parameter    SDRAM_READ_LATENCY    = 2,
47
    parameter    SDRAM_TARGET          = "XILINX"
48
)
49
 
50
//-----------------------------------------------------------------
51
// Ports
52
//-----------------------------------------------------------------
53
(
54
    input           clk_i,
55
    input           rst_i,
56
 
57
    // Wishbone Interface
58
    input           stb_i,
59
    input           we_i,
60
    input [3:0]     sel_i,
61
    input           cyc_i,
62
    input [31:0]    addr_i,
63
    input [31:0]    data_i,
64
    output [31:0]   data_o,
65
    output          stall_o,
66
    output          ack_o,
67
 
68
    // SDRAM Interface
69
    output          sdram_clk_o,
70
    output          sdram_cke_o,
71
    output          sdram_cs_o,
72
    output          sdram_ras_o,
73
    output          sdram_cas_o,
74
    output          sdram_we_o,
75
    output [1:0]    sdram_dqm_o,
76
    output [12:0]   sdram_addr_o,
77
    output [1:0]    sdram_ba_o,
78
    inout [15:0]    sdram_data_io
79
);
80
 
81
//-----------------------------------------------------------------
82
// Defines / Local params
83
//-----------------------------------------------------------------
84
localparam CMD_W             = 4;
85
localparam CMD_NOP           = 4'b0111;
86
localparam CMD_ACTIVE        = 4'b0011;
87
localparam CMD_READ          = 4'b0101;
88
localparam CMD_WRITE         = 4'b0100;
89
localparam CMD_TERMINATE     = 4'b0110;
90
localparam CMD_PRECHARGE     = 4'b0010;
91
localparam CMD_REFRESH       = 4'b0001;
92
localparam CMD_LOAD_MODE     = 4'b0000;
93
 
94
// Mode: Burst Length = 4 bytes, CAS=2
95
localparam MODE_REG          = {3'b000,1'b0,2'b00,3'b010,1'b0,3'b001};
96
 
97
// SM states
98
localparam STATE_W           = 4;
99
localparam STATE_INIT        = 4'd0;
100
localparam STATE_DELAY       = 4'd1;
101
localparam STATE_IDLE        = 4'd2;
102
localparam STATE_ACTIVATE    = 4'd3;
103
localparam STATE_READ        = 4'd4;
104
localparam STATE_READ_WAIT   = 4'd5;
105
localparam STATE_WRITE0      = 4'd6;
106
localparam STATE_WRITE1      = 4'd7;
107
localparam STATE_PRECHARGE   = 4'd8;
108
localparam STATE_REFRESH     = 4'd9;
109
 
110
localparam AUTO_PRECHARGE    = 10;
111
localparam ALL_BANKS         = 10;
112
 
113
localparam SDRAM_DATA_W      = 16;
114
 
115
localparam CYCLE_TIME_NS     = 1000 / SDRAM_MHZ;
116
 
117
// SDRAM timing
118
localparam SDRAM_TRCD_CYCLES = (20 + (CYCLE_TIME_NS-1)) / CYCLE_TIME_NS;
119
localparam SDRAM_TRP_CYCLES  = (20 + (CYCLE_TIME_NS-1)) / CYCLE_TIME_NS;
120
localparam SDRAM_TRFC_CYCLES = (60 + (CYCLE_TIME_NS-1)) / CYCLE_TIME_NS;
121
 
122
//-----------------------------------------------------------------
123
// Registers / Wires
124
//-----------------------------------------------------------------
125
 
126
// Xilinx placement pragmas:
127
//synthesis attribute IOB of command_q is "TRUE"
128
//synthesis attribute IOB of addr_q is "TRUE"
129
//synthesis attribute IOB of dqm_q is "TRUE"
130
//synthesis attribute IOB of cke_q is "TRUE"
131
//synthesis attribute IOB of bank_q is "TRUE"
132
//synthesis attribute IOB of data_q is "TRUE"
133
 
134
reg [CMD_W-1:0]        command_q;
135
reg [SDRAM_ROW_W-1:0]  addr_q;
136
reg [SDRAM_DATA_W-1:0] data_q;
137
reg                    data_rd_en_q;
138
reg [SDRAM_DQM_W-1:0]  dqm_q;
139
reg                    cke_q;
140
reg [SDRAM_BANK_W-1:0] bank_q;
141
 
142
// Buffer half word during read and write commands
143
reg [SDRAM_DATA_W-1:0] data_buffer_q;
144
reg [SDRAM_DQM_W-1:0]  dqm_buffer_q;
145
 
146
wire [SDRAM_DATA_W-1:0] sdram_data_in_w;
147
 
148
reg                    refresh_q;
149
 
150
reg [SDRAM_BANKS-1:0]  row_open_q;
151
reg [SDRAM_ROW_W-1:0]  active_row_q[0:SDRAM_BANKS-1];
152
 
153
reg  [STATE_W-1:0]     state_q;
154
reg  [STATE_W-1:0]     next_state_r;
155
reg  [STATE_W-1:0]     target_state_r;
156
reg  [STATE_W-1:0]     target_state_q;
157
reg  [STATE_W-1:0]     delay_state_q;
158
 
159
// Address bits
160
wire [SDRAM_ROW_W-1:0]  addr_col_w  = {{(SDRAM_ROW_W-SDRAM_COL_W){1'b0}}, addr_i[SDRAM_COL_W:2], 1'b0};
161
wire [SDRAM_ROW_W-1:0]  addr_row_w  = addr_i[SDRAM_ADDR_W:SDRAM_COL_W+2+1];
162
wire [SDRAM_BANK_W-1:0] addr_bank_w = addr_i[SDRAM_COL_W+2:SDRAM_COL_W+2-1];
163
 
164
//-----------------------------------------------------------------
165
// SDRAM State Machine
166
//-----------------------------------------------------------------
167
always @ *
168
begin
169
    next_state_r   = state_q;
170
    target_state_r = target_state_q;
171
 
172
    case (state_q)
173
    //-----------------------------------------
174
    // STATE_INIT
175
    //-----------------------------------------
176
    STATE_INIT :
177
    begin
178
        if (refresh_q)
179
            next_state_r = STATE_IDLE;
180
    end
181
    //-----------------------------------------
182
    // STATE_IDLE
183
    //-----------------------------------------
184
    STATE_IDLE :
185
    begin
186
        // Pending refresh
187
        // Note: tRAS (open row time) cannot be exceeded due to periodic
188
        //        auto refreshes.
189
        if (refresh_q)
190
        begin
191
            // Close open rows, then refresh
192
            if (|row_open_q)
193
                next_state_r = STATE_PRECHARGE;
194
            else
195
                next_state_r = STATE_REFRESH;
196
 
197
            target_state_r = STATE_REFRESH;
198
        end
199
        // Access request
200
        else if (stb_i && cyc_i)
201
        begin
202
            // Open row hit
203
            if (row_open_q[addr_bank_w] && addr_row_w == active_row_q[addr_bank_w])
204
            begin
205
                if (we_i)
206
                    next_state_r = STATE_WRITE0;
207
                else
208
                    next_state_r = STATE_READ;
209
            end
210
            // Row miss, close row, open new row
211
            else if (row_open_q[addr_bank_w])
212
            begin
213
                next_state_r   = STATE_PRECHARGE;
214
 
215
                if (we_i)
216
                    target_state_r = STATE_WRITE0;
217
                else
218
                    target_state_r = STATE_READ;
219
            end
220
            // No open row, open row
221
            else
222
            begin
223
                next_state_r   = STATE_ACTIVATE;
224
 
225
                if (we_i)
226
                    target_state_r = STATE_WRITE0;
227
                else
228
                    target_state_r = STATE_READ;
229
            end
230
        end
231
    end
232
    //-----------------------------------------
233
    // STATE_ACTIVATE
234
    //-----------------------------------------
235
    STATE_ACTIVATE :
236
    begin
237
        // Proceed to read or write state
238
        next_state_r = target_state_r;
239
    end
240
    //-----------------------------------------
241
    // STATE_READ
242
    //-----------------------------------------
243
    STATE_READ :
244
    begin
245
        next_state_r = STATE_READ_WAIT;
246
    end
247
    //-----------------------------------------
248
    // STATE_READ_WAIT
249
    //-----------------------------------------
250
    STATE_READ_WAIT :
251
    begin
252
        next_state_r = STATE_IDLE;
253
 
254
        // Another pending read request (with no refresh pending)
255
        if (!refresh_q && stb_i && cyc_i && !we_i)
256
        begin
257
            // Open row hit
258
            if (row_open_q[addr_bank_w] && addr_row_w == active_row_q[addr_bank_w])
259
                next_state_r = STATE_READ;
260
        end
261
    end
262
    //-----------------------------------------
263
    // STATE_WRITE0
264
    //-----------------------------------------
265
    STATE_WRITE0 :
266
    begin
267
        next_state_r = STATE_WRITE1;
268
    end
269
    //-----------------------------------------
270
    // STATE_WRITE1
271
    //-----------------------------------------
272
    STATE_WRITE1 :
273
    begin
274
        next_state_r = STATE_IDLE;
275
 
276
        // Another pending write request (with no refresh pending)
277
        if (!refresh_q && stb_i && cyc_i && we_i)
278
        begin
279
            // Open row hit
280
            if (row_open_q[addr_bank_w] && addr_row_w == active_row_q[addr_bank_w])
281
                next_state_r = STATE_WRITE0;
282
        end
283
    end
284
    //-----------------------------------------
285
    // STATE_PRECHARGE
286
    //-----------------------------------------
287
    STATE_PRECHARGE :
288
    begin
289
        // Closing row to perform refresh
290
        if (target_state_r == STATE_REFRESH)
291
            next_state_r = STATE_REFRESH;
292
        // Must be closing row to open another
293
        else
294
            next_state_r = STATE_ACTIVATE;
295
    end
296
    //-----------------------------------------
297
    // STATE_REFRESH
298
    //-----------------------------------------
299
    STATE_REFRESH :
300
    begin
301
        next_state_r = STATE_IDLE;
302
    end
303
    //-----------------------------------------
304
    // STATE_DELAY
305
    //-----------------------------------------
306
    STATE_DELAY :
307
    begin
308
        next_state_r = delay_state_q;
309
    end
310
    default:
311
        ;
312
   endcase
313
end
314
 
315
//-----------------------------------------------------------------
316
// Delays
317
//-----------------------------------------------------------------
318
localparam DELAY_W = 4;
319
 
320
reg [DELAY_W-1:0] delay_q;
321
reg [DELAY_W-1:0] delay_r;
322
 
323
/* verilator lint_off WIDTH */
324
 
325
always @ *
326
begin
327
    case (state_q)
328
    //-----------------------------------------
329
    // STATE_ACTIVATE
330
    //-----------------------------------------
331
    STATE_ACTIVATE :
332
    begin
333
        // tRCD (ACTIVATE -> READ / WRITE)
334
        delay_r = SDRAM_TRCD_CYCLES;
335
    end
336
    //-----------------------------------------
337
    // STATE_READ_WAIT
338
    //-----------------------------------------
339
    STATE_READ_WAIT :
340
    begin
341
        delay_r = SDRAM_READ_LATENCY;
342
 
343
        // Another pending read request (with no refresh pending)
344
        if (!refresh_q && stb_i && cyc_i && !we_i)
345
        begin
346
            // Open row hit
347
            if (row_open_q[addr_bank_w] && addr_row_w == active_row_q[addr_bank_w])
348
                delay_r = 4'd0;
349
        end
350
    end
351
    //-----------------------------------------
352
    // STATE_PRECHARGE
353
    //-----------------------------------------
354
    STATE_PRECHARGE :
355
    begin
356
        // tRP (PRECHARGE -> ACTIVATE)
357
        delay_r = SDRAM_TRP_CYCLES;
358
    end
359
    //-----------------------------------------
360
    // STATE_REFRESH
361
    //-----------------------------------------
362
    STATE_REFRESH :
363
    begin
364
        // tRFC
365
        delay_r = SDRAM_TRFC_CYCLES;
366
    end
367
    //-----------------------------------------
368
    // STATE_DELAY
369
    //-----------------------------------------
370
    STATE_DELAY:
371
    begin
372
        delay_r = delay_q - 4'd1;
373
    end
374
    //-----------------------------------------
375
    // Others
376
    //-----------------------------------------
377
    default:
378
    begin
379
        delay_r = {DELAY_W{1'b0}};
380
    end
381
    endcase
382
end
383
/* verilator lint_on WIDTH */
384
 
385
// Record target state
386
always @ (posedge rst_i or posedge clk_i)
387
if (rst_i)
388
    target_state_q   <= STATE_IDLE;
389
else
390
    target_state_q   <= target_state_r;
391
 
392
// Record delayed state
393
always @ (posedge rst_i or posedge clk_i)
394
if (rst_i)
395
    delay_state_q   <= STATE_IDLE;
396
// On entering into delay state, record intended next state
397
else if (state_q != STATE_DELAY && delay_r != {DELAY_W{1'b0}})
398
    delay_state_q   <= next_state_r;
399
 
400
// Update actual state
401
always @ (posedge rst_i or posedge clk_i)
402
if (rst_i)
403
    state_q   <= STATE_INIT;
404
// Delaying...
405
else if (delay_r != {DELAY_W{1'b0}})
406
    state_q   <= STATE_DELAY;
407
else
408
    state_q   <= next_state_r;
409
 
410
// Update delay flops
411
always @ (posedge rst_i or posedge clk_i)
412
if (rst_i)
413
    delay_q   <= {DELAY_W{1'b0}};
414
else
415
    delay_q   <= delay_r;
416
 
417
//-----------------------------------------------------------------
418
// Refresh counter
419
//-----------------------------------------------------------------
420
localparam REFRESH_CNT_W = 17;
421
 
422
reg [REFRESH_CNT_W-1:0] refresh_timer_q;
423
always @ (posedge rst_i or posedge clk_i)
424
if (rst_i)
425
    refresh_timer_q <= SDRAM_START_DELAY + 100;
426
else if (refresh_timer_q == {REFRESH_CNT_W{1'b0}})
427
    refresh_timer_q <= SDRAM_REFRESH_CYCLES;
428
else
429
    refresh_timer_q <= refresh_timer_q - 1;
430
 
431
always @ (posedge rst_i or posedge clk_i)
432
if (rst_i)
433
    refresh_q <= 1'b0;
434
else if (refresh_timer_q == {REFRESH_CNT_W{1'b0}})
435
    refresh_q <= 1'b1;
436
else if (state_q == STATE_REFRESH)
437
    refresh_q <= 1'b0;
438
 
439
//-----------------------------------------------------------------
440
// Input sampling
441
//-----------------------------------------------------------------
442
 
443
reg [SDRAM_DATA_W-1:0] sample_data0_q;
444
always @ (posedge rst_i or posedge clk_i)
445
if (rst_i)
446
    sample_data0_q <= {SDRAM_DATA_W{1'b0}};
447
else
448
    sample_data0_q <= sdram_data_in_w;
449
 
450
reg [SDRAM_DATA_W-1:0] sample_data_q;
451
always @ (posedge rst_i or posedge clk_i)
452
if (rst_i)
453
    sample_data_q <= {SDRAM_DATA_W{1'b0}};
454
else
455
    sample_data_q <= sample_data0_q;
456
 
457
//-----------------------------------------------------------------
458
// Command Output
459
//-----------------------------------------------------------------
460
integer idx;
461
 
462
always @ (posedge rst_i or posedge clk_i)
463
if (rst_i)
464
begin
465
    command_q       <= CMD_NOP;
466
    data_q          <= 16'b0;
467
    addr_q          <= {SDRAM_ROW_W{1'b0}};
468
    bank_q          <= {SDRAM_BANK_W{1'b0}};
469
    cke_q           <= 1'b0;
470
    dqm_q           <= {SDRAM_DQM_W{1'b0}};
471
    data_rd_en_q    <= 1'b1;
472
    dqm_buffer_q    <= {SDRAM_DQM_W{1'b0}};
473
 
474
    for (idx=0;idx<SDRAM_BANKS;idx=idx+1)
475
        active_row_q[idx] <= {SDRAM_ROW_W{1'b0}};
476
 
477
    row_open_q      <= {SDRAM_BANKS{1'b0}};
478
end
479
else
480
begin
481
    case (state_q)
482
    //-----------------------------------------
483
    // STATE_IDLE / Default (delays)
484
    //-----------------------------------------
485
    default:
486
    begin
487
        // Default
488
        command_q    <= CMD_NOP;
489
        addr_q       <= {SDRAM_ROW_W{1'b0}};
490
        bank_q       <= {SDRAM_BANK_W{1'b0}};
491
        data_rd_en_q <= 1'b1;
492
    end
493
    //-----------------------------------------
494
    // STATE_INIT
495
    //-----------------------------------------
496
    STATE_INIT:
497
    begin
498
        // Assert CKE
499
        if (refresh_timer_q == 50)
500
        begin
501
            // Assert CKE after 100uS
502
            cke_q <= 1'b1;
503
        end
504
        // PRECHARGE
505
        else if (refresh_timer_q == 40)
506
        begin
507
            // Precharge all banks
508
            command_q           <= CMD_PRECHARGE;
509
            addr_q[ALL_BANKS]   <= 1'b1;
510
        end
511
        // 2 x REFRESH (with at least tREF wait)
512
        else if (refresh_timer_q == 20 || refresh_timer_q == 30)
513
        begin
514
            command_q <= CMD_REFRESH;
515
        end
516
        // Load mode register
517
        else if (refresh_timer_q == 10)
518
        begin
519
            command_q <= CMD_LOAD_MODE;
520
            addr_q    <= MODE_REG;
521
        end
522
        // Other cycles during init - just NOP
523
        else
524
        begin
525
            command_q   <= CMD_NOP;
526
            addr_q      <= {SDRAM_ROW_W{1'b0}};
527
            bank_q      <= {SDRAM_BANK_W{1'b0}};
528
        end
529
    end
530
    //-----------------------------------------
531
    // STATE_ACTIVATE
532
    //-----------------------------------------
533
    STATE_ACTIVATE :
534
    begin
535
        // Select a row and activate it
536
        command_q     <= CMD_ACTIVE;
537
        addr_q        <= addr_row_w;
538
        bank_q        <= addr_bank_w;
539
 
540
        active_row_q[addr_bank_w]  <= addr_row_w;
541
        row_open_q[addr_bank_w]    <= 1'b1;
542
    end
543
    //-----------------------------------------
544
    // STATE_PRECHARGE
545
    //-----------------------------------------
546
    STATE_PRECHARGE :
547
    begin
548
        // Precharge due to refresh, close all banks
549
        if (target_state_r == STATE_REFRESH)
550
        begin
551
            // Precharge all banks
552
            command_q           <= CMD_PRECHARGE;
553
            addr_q[ALL_BANKS]   <= 1'b1;
554
            row_open_q          <= {SDRAM_BANKS{1'b0}};
555
        end
556
        else
557
        begin
558
            // Precharge specific banks
559
            command_q           <= CMD_PRECHARGE;
560
            addr_q[ALL_BANKS]   <= 1'b0;
561
            bank_q              <= addr_bank_w;
562
 
563
            row_open_q[addr_bank_w] <= 1'b0;
564
        end
565
    end
566
    //-----------------------------------------
567
    // STATE_REFRESH
568
    //-----------------------------------------
569
    STATE_REFRESH :
570
    begin
571
        // Auto refresh
572
        command_q   <= CMD_REFRESH;
573
        addr_q      <= {SDRAM_ROW_W{1'b0}};
574
        bank_q      <= {SDRAM_BANK_W{1'b0}};
575
    end
576
    //-----------------------------------------
577
    // STATE_READ
578
    //-----------------------------------------
579
    STATE_READ :
580
    begin
581
        command_q   <= CMD_READ;
582
        addr_q      <= addr_col_w;
583
        bank_q      <= addr_bank_w;
584
 
585
        // Disable auto precharge (auto close of row)
586
        addr_q[AUTO_PRECHARGE]  <= 1'b0;
587
 
588
        // Read mask (all bytes in burst)
589
        dqm_q       <= {SDRAM_DQM_W{1'b0}};
590
    end
591
    //-----------------------------------------
592
    // STATE_WRITE0
593
    //-----------------------------------------
594
    STATE_WRITE0 :
595
    begin
596
        command_q       <= CMD_WRITE;
597
        addr_q          <= addr_col_w;
598
        bank_q          <= addr_bank_w;
599
        data_q          <= data_i[15:0];
600
 
601
        // Disable auto precharge (auto close of row)
602
        addr_q[AUTO_PRECHARGE]  <= 1'b0;
603
 
604
        // Write mask
605
        dqm_q           <= ~sel_i[1:0];
606
        dqm_buffer_q    <= ~sel_i[3:2];
607
 
608
        data_rd_en_q    <= 1'b0;
609
    end
610
    //-----------------------------------------
611
    // STATE_WRITE1
612
    //-----------------------------------------
613
    STATE_WRITE1 :
614
    begin
615
        // Burst continuation
616
        command_q   <= CMD_NOP;
617
 
618
        data_q      <= data_buffer_q;
619
 
620
        // Disable auto precharge (auto close of row)
621
        addr_q[AUTO_PRECHARGE]  <= 1'b0;
622
 
623
        // Write mask
624
        dqm_q       <= dqm_buffer_q;
625
    end
626
    endcase
627
end
628
 
629
//-----------------------------------------------------------------
630
// Record read events
631
//-----------------------------------------------------------------
632
reg [SDRAM_READ_LATENCY+1:0]  rd_q;
633
 
634
always @ (posedge rst_i or posedge clk_i)
635
if (rst_i)
636
    rd_q    <= {(SDRAM_READ_LATENCY+2){1'b0}};
637
else
638
    rd_q    <= {rd_q[SDRAM_READ_LATENCY:0], (state_q == STATE_READ)};
639
 
640
//-----------------------------------------------------------------
641
// Data Buffer
642
//-----------------------------------------------------------------
643
 
644
// Buffer upper 16-bits of write data so write command can be accepted
645
// in WRITE0. Also buffer lower 16-bits of read data.
646
always @ (posedge rst_i or posedge clk_i)
647
if (rst_i)
648
    data_buffer_q <= 16'b0;
649
else if (state_q == STATE_WRITE0)
650
    data_buffer_q <= data_i[31:16];
651
else if (rd_q[SDRAM_READ_LATENCY+1])
652
    data_buffer_q <= sample_data_q;
653
 
654
// Read data output
655
assign data_o = {sample_data_q, data_buffer_q};
656
 
657
//-----------------------------------------------------------------
658
// Wishbone ACK
659
//-----------------------------------------------------------------
660
reg ack_q;
661
 
662
always @ (posedge rst_i or posedge clk_i)
663
if (rst_i)
664
    ack_q   <= 1'b0;
665
else
666
begin
667
    if (state_q == STATE_WRITE1)
668
        ack_q <= 1'b1;
669
    else if (rd_q[SDRAM_READ_LATENCY+1])
670
        ack_q <= 1'b1;
671
    else
672
        ack_q <= 1'b0;
673
end
674
 
675
assign ack_o  = ack_q;
676
 
677
// Accept wishbone command in READ or WRITE0 states
678
assign stall_o = ~(state_q == STATE_READ || state_q == STATE_WRITE0);
679
 
680
//-----------------------------------------------------------------
681
// SDRAM I/O
682
//-----------------------------------------------------------------
683
genvar i;
684
 
685
generate
686
if (SDRAM_TARGET == "XILINX")
687
begin
688
    // 180 degree phase delayed sdram clock output
689
    ODDR2
690
    #(
691
        .DDR_ALIGNMENT("NONE"),
692
        .INIT(1'b0),
693
        .SRTYPE("SYNC")
694
    )
695
    u_clock_delay
696
    (
697
        .Q(sdram_clk_o),
698
        .C0(clk_i),
699
        .C1(~clk_i),
700
        .CE(1'b1),
701
        .R(1'b0),
702
        .S(1'b0),
703
        .D0(1'b0),
704
        .D1(1'b1)
705
    );
706
 
707
    for (i=0; i < 16; i = i + 1)
708
    begin
709
      IOBUF
710
      #(
711
        .DRIVE(12),
712
        .IOSTANDARD("LVTTL"),
713
        .SLEW("FAST")
714
      )
715
      u_data_buf
716
      (
717
        .O(sdram_data_in_w[i]),
718
        .IO(sdram_data_io[i]),
719
        .I(data_q[i]),
720
        .T(data_rd_en_q)
721
      );
722
    end
723
end
724
else
725
begin
726
    assign sdram_clk_o     = ~clk_i;
727
    assign sdram_data_io   = data_rd_en_q ? 16'bz : data_q;
728
    assign sdram_data_in_w = sdram_data_io;
729
end
730
endgenerate
731
 
732
assign sdram_cke_o  = cke_q;
733
assign sdram_cs_o   = command_q[3];
734
assign sdram_ras_o  = command_q[2];
735
assign sdram_cas_o  = command_q[1];
736
assign sdram_we_o   = command_q[0];
737
assign sdram_dqm_o  = dqm_q;
738
assign sdram_ba_o   = bank_q;
739
assign sdram_addr_o = addr_q;
740
 
741
endmodule

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