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[/] [sdram_16bit/] [trunk/] [testbench/] [IS42VM16400K.v] - Blame information for rev 2

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1 2 ultra_embe 
/************************************************************************
2 
*
3 
* Copyright(c) ISSI Inc., 2010
4 
*
5 
* == 64M Low power SDRAM behavioral Model by ESC ==
6 
*
7 
* Address : 1940 Zanker Road San Jose,CA95112-4216,U.S.A.
8 
* Tel : +1-408-969-6600, Fax : +1-408-969-7800
9 
*
10 
* Revision : Rev0.0 (2010.10.4)
11 
*
12 
* Running Options
13 
*  +S50     : Set AC timing parameter for -50(200MHz  )
14 
*  +S60     : Set AC timing parameter for -60(166MHz  )
15 
*  +S75     : Set AC timing parameter for -75(133MHz  )
16 
*  +VERBOSE : Display internal operation status
17 
*
18 
************************************************************************/
19 
 
20 
`timescale 1ns / 1ps
21 
 
22 
`define S60
23 
//`define VERBOSE
24 
 
25 
    module IS42VM16400K (dq, addr, ba, clk, cke, csb, rasb, casb, web, dqm);
26 
 
27 
    parameter no_of_bank =       2;
28 
    parameter no_of_addr =      13;
29 
    parameter no_of_data =      16;
30 
    parameter no_of_col  =       9;
31 
    parameter no_of_dqm  =       2;
32 
    parameter mem_sizes  = 4194304;
33 
 
34 
 
35 
    // Timing Parameters for -50 PC200
36 
    `ifdef S50
37 
    parameter tAC3 =   5.0;
38 
    parameter tHZ3 =   5.0;
39 
    parameter tAC2 =   8.0;
40 
    parameter tHZ2 =   8.0;
41 
    parameter tOH  =   2.0;
42 
    parameter tMRD =   2.0;
43 
    parameter tRAS =  40.0;
44 
    parameter tRC  =  55.0;
45 
    parameter tRCD =  18.0;
46 
    parameter tRFC =  60.0;
47 
    parameter tXSR =  60.0;
48 
    parameter tRP  =  15.0;
49 
    parameter tRRD =  10.0;
50 
    parameter tDPLa =  5.0;
51 
    parameter tDPLm =  12.0;
52 
    parameter tDPDX =  100000.0;
53 
    `endif
54 
 
55 
 
56 
    // Timing Parameters for -60 PC166
57 
    `ifdef S60
58 
    parameter tAC3 =   5.5;
59 
    parameter tHZ3 =   5.5;
60 
    parameter tAC2 =   8.0;
61 
    parameter tHZ2 =   8.0;
62 
    parameter tOH  =   2.5;
63 
    parameter tMRD =   2.0;
64 
    parameter tRAS =  42.0;
65 
    parameter tRC  =  60.0;
66 
    parameter tRCD =  18.0;
67 
    parameter tRFC =  66.0;
68 
    parameter tXSR =  66.0;
69 
    parameter tRP  =  18.0;
70 
    parameter tRRD =  12.0;
71 
    parameter tDPLa =  6.0;
72 
    parameter tDPLm =  12.0;
73 
    parameter tDPDX =  100000.0;
74 
    `endif
75 
 
76 
    // Timing Parameters for -75 PC133
77 
    `ifdef S75
78 
    parameter tAC3 =   6.0;
79 
    parameter tHZ3 =   6.0;
80 
    parameter tAC2 =   8.0;
81 
    parameter tHZ2 =   8.0;
82 
    parameter tOH  =   2.5;
83 
    parameter tMRD =   2.0;
84 
    parameter tRAS =  45.0;
85 
    parameter tRC  =  67.5;
86 
    parameter tRCD =  22.5;
87 
    parameter tRFC =  67.5;
88 
    parameter tXSR =  67.5;
89 
    parameter tRP  =  22.5;
90 
    parameter tRRD =  15.0;
91 
    parameter tDPLa =  7.5;
92 
    parameter tDPLm =  15.0;
93 
    parameter tDPDX =  100000.0;
94 
    `endif
95 
 
96 
 
97 
    inout     [no_of_data - 1 : 0] dq;
98 
    input     [no_of_addr - 1 : 0] addr;
99 
    input     [no_of_bank - 1 : 0] ba;
100 
    input                         clk;
101 
    input                         cke;
102 
    input                         csb;
103 
    input                         rasb;
104 
    input                         casb;
105 
    input                         web;
106 
    input     [no_of_dqm - 1 : 0]  dqm;
107 
 
108 
`protect
109 
 
110 
    reg       [no_of_data - 1 : 0] bank0 [0 : mem_sizes];
111 
    reg       [no_of_data - 1 : 0] bank1 [0 : mem_sizes];
112 
    reg       [no_of_data - 1 : 0] bank2 [0 : mem_sizes];
113 
    reg       [no_of_data - 1 : 0] bank3 [0 : mem_sizes];
114 
 
115 
    reg       [no_of_bank - 1 : 0] bank_addr [0 : 3];                 // bank address Pipeline
116 
    reg       [no_of_col - 1 : 0] Col_addr [0 : 3];                 // Column address Pipeline
117 
    reg                   [3 : 0] Command [0 : 3];                  // Command Operation Pipeline
118 
    reg       [no_of_dqm - 1 : 0] dqm_reg0, dqm_reg1;               // DQM Operation Pipeline
119 
    reg       [no_of_dqm - 1 : 0] dqm_save [0 : 3];                 // DQM Operation Pipeline
120 
    reg       [no_of_addr - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
121 
 
122 
    reg       [no_of_addr - 1 : 0] Mode_reg;
123 
    reg       [no_of_addr - 1 : 0] EMode_reg;
124 
    reg       [no_of_data - 1 : 0] dq_reg, dq_dqm;
125 
    reg        [no_of_col - 1 : 0] Col_temp, Burst_counter;
126 
 
127 
    reg                           Act_b0, Act_b1, Act_b2, Act_b3;    // bank Activate
128 
    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;        // bank Precharge
129 
 
130 
    reg                   [1 : 0] bank_precharge       [0 : 3];     // Precharge Command
131 
    reg                           A10_precharge        [0 : 3];     // addr[10] = 1 (All banks)
132 
    reg                           Auto_precharge       [0 : 3];     // RW Auto Precharge (bank)
133 
    reg                           Read_precharge       [0 : 3];     // R  Auto Precharge
134 
    reg                           Write_precharge      [0 : 3];     //  W Auto Precharge
135 
    reg                           RW_interrupt_read    [0 : 3];     // RW Interrupt Read with Auto Precharge
136 
    reg                           RW_interrupt_write   [0 : 3];     // RW Interrupt Write with Auto Precharge
137 
    reg                   [1 : 0] RW_interrupt_bank;                // RW Interrupt bank
138 
    integer                       RW_interrupt_counter [0 : 3];     // RW Interrupt Counter
139 
    integer                       Count_precharge      [0 : 3];     // RW Auto Precharge Counter
140 
 
141 
    reg                           Data_in_enable;
142 
    reg                           Data_out_enable;
143 
 
144 
    reg       [no_of_bank - 1 : 0] bank, Prev_bank;
145 
    reg       [no_of_addr - 1 : 0] Row;
146 
    reg        [no_of_col - 1 : 0] Col, Col_brst;
147 
 
148 
    reg                 [19:0]    ccc;
149 
    reg                 [3:0]     bit;
150 
    reg                 [2:0]     CL;
151 
    reg                 [8:0]     BL;
152 
    reg             RIW_violate;
153 
    reg             Dout_Drive_Flag;
154 
    reg             Pre_Dout_Drive_Flag;
155 
    reg             [10:0] Count_at_Read;
156 
    reg             Read_cmd_received;
157 
    reg             Read_cmd_received_cke;
158 
    reg             Write_cmd_received_cke;
159 
    reg             state_act_pwrdn,state_pre_pwrdn,state_dpdn,state_self;
160 
    reg             dpdn_check_start;
161 
    reg             [10:0] Read_cmd_count;
162 
    reg             [10:0] Read_cmd_count_cke;
163 
    reg             [10:0] Write_cmd_count_cke;
164 
    reg             [3:0] cmp_count;
165 
    // Internal system clock
166 
    reg                           ckeZ, Sys_clk;
167 
 
168 
    // Commands Decode
169 
    wire      Active_enable    = ~csb & ~rasb &  casb &  web ;
170 
    wire      Aref_enable      = ~csb & ~rasb & ~casb &  web & cke;
171 
    wire      Sref_enable      = ~csb & ~rasb & ~casb &  web & ~cke;
172 
    wire      Burst_term       = ~csb &  rasb &  casb & ~web & cke;
173 
    wire      Deep_pwrdn       = ~csb &  rasb &  casb & ~web & ~cke;
174 
    wire      Mode_reg_enable  = ~csb & ~rasb & ~casb & ~web & ~ba[1] & ~ba[0];
175 
    wire      EMode_reg_enable = ~csb & ~rasb & ~casb & ~web & ba[1] & ~ba[0];
176 
    wire      Prech_enable     = ~csb & ~rasb &  casb & ~web ;
177 
    wire      Read_enable      = ~csb &  rasb & ~casb &  web ;
178 
    wire      Write_enable     = ~csb &  rasb & ~casb & ~web ;
179 
 
180 
    // Burst Length Decode
181 
    wire      Burst_length_1   = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
182 
    wire      Burst_length_2   = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
183 
    wire      Burst_length_4   = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
184 
    wire      Burst_length_8   = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
185 
    wire      Burst_length_f   =  Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
186 
 
187 
    // CAS Latency Decode
188 
    wire      Cas_latency_1    = ~Mode_reg[6] & ~Mode_reg[5] &  Mode_reg[4];
189 
    wire      Cas_latency_2    = ~Mode_reg[6] &  Mode_reg[5] & ~Mode_reg[4];
190 
    wire      Cas_latency_3    = ~Mode_reg[6] &  Mode_reg[5] &  Mode_reg[4];
191 
 
192 
    // Write Burst Mode
193 
    wire      Write_burst_mode = Mode_reg[9];
194 
 
195 
`ifdef VERBOSE
196 
    wire      Debug            = 1'b1;                          // Debug messages : 1 = On
197 
`else
198 
    wire      Debug            = 1'b0;                          // Debug messages : 1 = On
199 
`endif
200 
 
201 
    wire      dq_chk           = Sys_clk & Data_in_enable;      // Check setup/hold time for DQ
202 
 
203 
    // CKE function
204 
    wire      clk_suspend_write= (Act_b0 | Act_b1 | Act_b2 | Act_b3) & Write_cmd_received_cke;
205 
    wire      clk_suspend_read = (Act_b0 | Act_b1 | Act_b2 | Act_b3) & Read_cmd_received_cke;
206 
    wire      act_pwrdn        = (Act_b0 | Act_b1 | Act_b2 | Act_b3) & (~Read_cmd_received_cke & ~Write_cmd_received_cke);
207 
    wire      pch_pwrdn        = (Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) & (~Read_cmd_received_cke | ~Write_cmd_received_cke);
208 
 
209 
    assign    dq               = dq_reg;                        // DQ buffer
210 
 
211 
    // Commands Operation
212 
    `define   ACT       0
213 
    `define   NOP       1
214 
    `define   READ      2
215 
    `define   WRITE     3
216 
    `define   PRECH     4
217 
    `define   A_REF     5
218 
    `define   BST       6
219 
    `define   LMR       7
220 
 
221 
    // Timing Check variable
222 
    real  MRD_chk;
223 
    real  WR_chkm0, WR_chkm1, WR_chkm2, WR_chkm3;
224 
    real  RFC_chk, RRD_chk;
225 
    real  RC_chk0, RC_chk1, RC_chk2, RC_chk3 ;
226 
    real  RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 ;
227 
    real  RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 ;
228 
    real  RP_chk0, RP_chk1, RP_chk2, RP_chk3 ;
229 
    real  SELF_chk, DPDN_chk ;
230 
 
231 
    initial begin
232 
        mem_init;
233 
        dq_reg = {no_of_data{1'bz}};
234 
        Data_in_enable = 0; Data_out_enable = 0;
235 
        Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
236 
        Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
237 
        WR_chkm0 = 0; WR_chkm1 = 0; WR_chkm2 = 0; WR_chkm3 = 0;
238 
        RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
239 
        RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
240 
        MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
241 
        RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
242 
        RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
243 
        RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
244 
        RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
245 
        SELF_chk = 0; DPDN_chk = 0;
246 
        Read_cmd_received=0;
247 
        Read_cmd_count=0;
248 
        Read_cmd_received_cke=0;
249 
        Read_cmd_count_cke=0;
250 
        Write_cmd_received_cke=0;
251 
        Write_cmd_count_cke=0;
252 
        state_act_pwrdn=0;
253 
        state_pre_pwrdn=0;
254 
        state_dpdn=0;
255 
        state_self=0;
256 
        dpdn_check_start=0;
257 
        EMode_reg=0;
258 
        Mode_reg=0;
259 
        Count_at_Read=0;
260 
 
261 
        $timeformat (-9, 2, " ns", 12);
262 
    end
263 
 
264 
    // System clock generator
265 
    always begin
266 
        @ (posedge clk) begin
267 
            Sys_clk = ckeZ;
268 
            ckeZ = cke;
269 
        end
270 
        @ (negedge clk) begin
271 
            Sys_clk = 1'b0;
272 
        end
273 
    end
274 
 
275 
    always @ (posedge clk) begin
276 
        // CKE Exit
277 
        if (cke === 1'b1) begin
278 
          if (state_self === 1'b1) begin
279 
            state_self = 1'b0;
280 
            SELF_chk=$realtime;
281 
            if (Debug) $display ("Time = %t : OPERATION = SREFX : Self Refresh exit", $realtime);
282 
          end else if (state_dpdn == 1'b1) begin
283 
            state_dpdn = 1'b0;
284 
            DPDN_chk=$realtime;
285 
            if (Debug) $display ("Time = %t : OPERATION = DPDNX : Deep Powerdown exit", $realtime);
286 
          end else if (state_act_pwrdn == 1'b1) begin
287 
            state_act_pwrdn = 1'b0;
288 
            if (Debug) $display ("Time = %t : OPERATION = APDNX : Active Power down exit", $realtime);
289 
          end else if (state_pre_pwrdn == 1'b1) begin
290 
            state_pre_pwrdn = 1'b0;
291 
            if (Debug) $display ("Time = %t : OPERATION = PPDNX : Precharge Power down exit", $realtime);
292 
          end
293 
        end
294 
    end
295 
 
296 
 
297 
    always @ (Dout_Drive_Flag) begin
298 
 
299 
        if(Cas_latency_2 ==1) begin
300 
 
301 
        Pre_Dout_Drive_Flag <= #tHZ2 Dout_Drive_Flag;
302 
 
303 
        end else if(Cas_latency_3 ==1) begin
304 
 
305 
        Pre_Dout_Drive_Flag <= #tHZ3 Dout_Drive_Flag;
306 
 
307 
        end
308 
 
309 
    end
310 
 
311 
 
312 
 
313 
 
314 
    always @ (posedge Sys_clk) begin
315 
        // Internal Commamd Pipelined
316 
        Command[0] = Command[1];
317 
        Command[1] = Command[2];
318 
        Command[2] = Command[3];
319 
        Command[3] = `NOP;
320 
 
321 
        Col_addr[0] = Col_addr[1];
322 
        Col_addr[1] = Col_addr[2];
323 
        Col_addr[2] = Col_addr[3];
324 
        Col_addr[3] = {no_of_col{1'b0}};
325 
 
326 
        bank_addr[0] = bank_addr[1];
327 
        bank_addr[1] = bank_addr[2];
328 
        bank_addr[2] = bank_addr[3];
329 
        bank_addr[3] = 2'b00;
330 
 
331 
        bank_precharge[0] = bank_precharge[1];
332 
        bank_precharge[1] = bank_precharge[2];
333 
        bank_precharge[2] = bank_precharge[3];
334 
        bank_precharge[3] = 2'b00;
335 
 
336 
        A10_precharge[0] = A10_precharge[1];
337 
        A10_precharge[1] = A10_precharge[2];
338 
        A10_precharge[2] = A10_precharge[3];
339 
        A10_precharge[3] = 1'b0;
340 
 
341 
        // dqm pipeline for Read
342 
        dqm_reg0 = dqm_reg1;
343 
        dqm_reg1 = dqm;
344 
 
345 
        dqm_save[3]=dqm_save[2];
346 
        dqm_save[2]=dqm_save[1];
347 
        dqm_save[1]=dqm_save[0];
348 
        dqm_save[0]=dqm;
349 
 
350 
 
351 
        if (Read_cmd_received == 1'b1) begin
352 
           Read_cmd_count = Read_cmd_count + 1;
353 
        end
354 
        else begin
355 
           Read_cmd_count = 4'b0;
356 
        end
357 
        //if (Read_cmd_count == (BL+CL+1)) begin
358 
        if (Read_cmd_count == Count_at_Read+(BL+CL+1)) begin
359 
           Read_cmd_received = 1'b0;
360 
        end
361 
 
362 
        // Count for CKE
363 
        if (Read_cmd_received_cke == 1'b1) begin
364 
           Read_cmd_count_cke = Read_cmd_count_cke + 1;
365 
        end
366 
        else begin
367 
           Read_cmd_count_cke = 4'b0;
368 
        end
369 
        if (Read_cmd_count_cke == (BL+CL-1)) begin
370 
           Read_cmd_received_cke = 1'b0;
371 
        end
372 
 
373 
        // Count for CKE
374 
        if (Write_cmd_received_cke == 1'b1) begin
375 
           Write_cmd_count_cke = Write_cmd_count_cke + 1;
376 
        end
377 
        else begin
378 
           Write_cmd_count_cke = 4'b0;
379 
        end
380 
        if (Write_cmd_count_cke == BL) begin
381 
           Write_cmd_received_cke = 1'b0;
382 
        end
383 
 
384 
 
385 
 
386 
        // Read or Write with Auto Precharge Counter
387 
        if (Auto_precharge[0] === 1'b1) begin
388 
            Count_precharge[0] = Count_precharge[0] + 1;
389 
        end
390 
        if (Auto_precharge[1] === 1'b1) begin
391 
            Count_precharge[1] = Count_precharge[1] + 1;
392 
        end
393 
        if (Auto_precharge[2] === 1'b1) begin
394 
            Count_precharge[2] = Count_precharge[2] + 1;
395 
        end
396 
        if (Auto_precharge[3] === 1'b1) begin
397 
            Count_precharge[3] = Count_precharge[3] + 1;
398 
        end
399 
 
400 
        // Read or Write Interrupt Counter
401 
        if (RW_interrupt_write[0] === 1'b1) begin
402 
            RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
403 
        end
404 
        if (RW_interrupt_write[1] === 1'b1) begin
405 
            RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
406 
        end
407 
        if (RW_interrupt_write[2] === 1'b1) begin
408 
            RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
409 
        end
410 
        if (RW_interrupt_write[3] === 1'b1) begin
411 
            RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
412 
        end
413 
 
414 
        // tMRD Counter
415 
        MRD_chk = MRD_chk + 1;
416 
 
417 
        // Auto Refresh
418 
        if (Aref_enable === 1'b1) begin
419 
            if (Debug) begin
420 
                //$display ("%m : at time %t AREF : Auto Refresh", $realtime);
421 
                $display ("Time = %t : OPERATION = AREF  : Auto Refresh", $realtime);
422 
            end
423 
 
424 
            // DPDXN to Auto Refresh
425 
            if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
426 
                $display ("Time = %t : ERROR : Pwrup violation(DPDX to AREF)", $realtime);
427 
            end
428 
 
429 
            // Self exit to Auto Refresh
430 
            if ($realtime - SELF_chk < tXSR) begin
431 
                $display ("Time = %t : ERROR : tXSR violation(SREFX to AREF)", $realtime);
432 
            end
433 
 
434 
            // Auto Refresh to Auto Refresh
435 
            if ($realtime - RFC_chk < tRFC) begin
436 
                //$display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $realtime);
437 
                $display ("Time = %t : ERROR : tRFC violation(AREF to AREF)", $realtime);
438 
            end
439 
 
440 
            // Precharge to Auto Refresh
441 
            if (($realtime - RP_chk0 < tRP)) begin
442 
                //$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
443 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE0 to AREF)", $realtime);
444 
            end
445 
            if (($realtime - RP_chk1 < tRP)) begin
446 
                //$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
447 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE1 to AREF)", $realtime);
448 
            end
449 
            if (($realtime - RP_chk2 < tRP)) begin
450 
                //$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
451 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE2 to AREF)", $realtime);
452 
            end
453 
            if (($realtime - RP_chk3 < tRP)) begin
454 
                //$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $realtime);
455 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE3 to AREF)", $realtime);
456 
            end
457 
 
458 
 
459 
            // Precharge to Refresh
460 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
461 
                //$display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $realtime);
462 
                $display ("Time = %t : ERROR : All banks must be Precharged before AREF", $realtime);
463 
            end
464 
 
465 
            // Load Mode Register to Auto Refresh
466 
            if (MRD_chk < tMRD) begin
467 
                //$display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $realtime);
468 
                $display ("Time = %t : ERROR : tMRD violation(MRS to AREF)", $realtime);
469 
            end
470 
 
471 
            // Record Current tRFC time
472 
            RFC_chk = $realtime;
473 
        end
474 
 
475 
        // Load Mode Register
476 
        if (Mode_reg_enable === 1'b1) begin
477 
            // Register Mode
478 
            Mode_reg = addr;
479 
 
480 
            // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
481 
            if (Debug) begin
482 
                //$display ("%m : at time %t LMR  : Load Mode Register", $realtime);
483 
                $display ("Time = %t : OPERATION = MRS   : Load Mode Register", $realtime);
484 
                // CAS Latency
485 
                case (addr[6 : 4])
486 
                    3'b010  : $display ("                                 CAS Latency      = 2");
487 
                    3'b011  : $display ("                                 CAS Latency      = 3");
488 
                    default : $display ("                                 CAS Latency      = Reserved");
489 
                endcase
490 
                case (addr[6 : 4])
491 
                    3'b010  : CL=2;
492 
                    3'b011  : CL=3;
493 
                    default : CL=3;
494 
                endcase
495 
 
496 
                // Burst Length
497 
                case (addr[2 : 0])
498 
                    3'b000  : $display ("                                 Burst Length     = 1");
499 
                    3'b001  : $display ("                                 Burst Length     = 2");
500 
                    3'b010  : $display ("                                 Burst Length     = 4");
501 
                    3'b011  : $display ("                                 Burst Length     = 8");
502 
                    3'b111  : $display ("                                 Burst Length     = Full");
503 
                    default : $display ("                                 Burst Length     = Reserved");
504 
                endcase
505 
 
506 
                case (addr[2 : 0])
507 
                    3'b000  : BL=1;
508 
                    3'b001  : BL=2;
509 
                    3'b010  : BL=4;
510 
                    3'b011  : BL=8;
511 
                    3'b111  : BL=512;
512 
                    default : BL=4;
513 
                endcase
514 
 
515 
 
516 
                // Burst Type
517 
                if (addr[3] === 1'b0) begin
518 
                    $display ("                                 Burst Type       = Sequential");
519 
                end else if (addr[3] === 1'b1) begin
520 
                    $display ("                                 Burst Type       = Interleaved");
521 
                end else begin
522 
                    $display ("                                 Burst Type       = Reserved");
523 
                end
524 
 
525 
                // Write Burst Mode
526 
                if (addr[9] === 1'b0) begin
527 
                    $display ("                                 Write Burst Mode = Programmed Burst Length");
528 
                end else if (addr[9] === 1'b1) begin
529 
                    $display ("                                 Write Burst Mode = Single Location Access");
530 
                end else begin
531 
                    $display ("                                 Write Burst Mode = Reserved");
532 
                end
533 
            end
534 
 
535 
            // Precharge to Load Mode Register
536 
            if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0 ) begin
537 
                //$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $realtime);
538 
                $display ("Time = %t : ERROR : all banks must be Precharge before Load Mode Register", $realtime);
539 
            end
540 
 
541 
            // Precharge to Load Mode Register
542 
            if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
543 
                ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
544 
                //$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $realtime);
545 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE to MRS)", $realtime);
546 
            end
547 
 
548 
            // Auto Refresh to Load Mode Register
549 
            if ($realtime - RFC_chk < tRFC) begin
550 
                //$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $realtime);
551 
                $display ("Time = %t : ERROR : tRFC violation(AREF to MRS)", $realtime);
552 
            end
553 
 
554 
            // Load Mode Register to Load Mode Register
555 
            if (MRD_chk < tMRD) begin
556 
                //$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $realtime);
557 
                $display ("Time = %t : ERROR : tMRD violation(MRS to MRS)", $realtime);
558 
            end
559 
 
560 
            // Reset MRD Counter
561 
            MRD_chk = 0;
562 
        end
563 
 
564 
        // Load Extended Mode Register
565 
        if (EMode_reg_enable === 1'b1) begin
566 
            // Register Mode
567 
            EMode_reg = addr;
568 
 
569 
            // Decode Driver Strength, Maximum Case Temp, Self Refresh Coverage
570 
            if (Debug) begin
571 
                //$display ("%m : at time %t LMR  : Load Mode Register", $realtime);
572 
                $display ("Time = %t : OPERATION = EMRS  : Load Extended Mode Register", $realtime);
573 
                // Driver Strength
574 
                case (addr[6 : 5])
575 
                    2'b00   : $display ("                                 Driver Strength        = Full");
576 
                    2'b01   : $display ("                                 Driver Strength        = 1/2");
577 
                    2'b10   : $display ("                                 Driver Strength        = 1/4");
578 
                    2'b11   : $display ("                                 Driver Strength        = 1/8");
579 
                    default : $display ("                                 Driver Strength        = Reserved");
580 
                endcase
581 
 
582 
                // Self Refresh Coverage
583 
                case (addr[2 : 0])
584 
                    3'b000   : $display ("                                 Self Refresh Coverage  = All Banks");
585 
                    3'b001   : $display ("                                 Self Refresh Coverage  = TWO Bank");
586 
                    3'b010   : $display ("                                 Self Refresh Coverage  = One Bank");
587 
                    3'b101   : $display ("                                 Self Refresh Coverage  = Half of one Banks");
588 
                    3'b110   : $display ("                                 Self Refresh Coverage  = Quater of one Banks");
589 
                    default  : $display ("                                 Self Refresh Coverage  = Reserved");
590 
                endcase
591 
 
592 
            end
593 
 
594 
            // Precharge to Load Mode Register
595 
            if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
596 
                //$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $realtime);
597 
                $display ("Time = %t : ERROR : all banks must be Precharge before Load Mode Register", $realtime);
598 
            end
599 
 
600 
            // Precharge to Load Mode Register
601 
            if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
602 
                ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
603 
                //$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $realtime);
604 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE to EMRS)", $realtime);
605 
            end
606 
 
607 
            // Auto Refresh to Load Mode Register
608 
            if ($realtime - RFC_chk < tRFC) begin
609 
                //$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $realtime);
610 
                $display ("Time = %t : ERROR : tRFC violation(AREF to EMRS)", $realtime);
611 
            end
612 
 
613 
            // Load Mode Register to Load Mode Register
614 
            if (MRD_chk < tMRD) begin
615 
                //$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $realtime);
616 
                $display ("Time = %t : ERROR : tMRD violation(MRS to EMRS)", $realtime);
617 
            end
618 
 
619 
            // Reset MRD Counter
620 
            MRD_chk = 0;
621 
        end
622 
 
623 
        // Active Block (Latch bank address and Row address)
624 
        if (Active_enable === 1'b1) begin
625 
            // Activate an open bank can corrupt data
626 
            if ((ba === 2'b00 && Act_b0 === 1'b1) || (ba === 2'b01 && Act_b1 === 1'b1) ||
627 
                (ba === 2'b10 && Act_b2 === 1'b1) || (ba === 2'b11 && Act_b3 === 1'b1)) begin
628 
                //$display ("%m : at time %t ERROR: bank already activated -- data can be corrupted", $realtime);
629 
                $display ("Time = %t : ERROR : bank already activated -- data could be corrupted", $realtime);
630 
               // $display ("Time = %t : Bank = %d, Act_b0 = %d, Act_b2 = %d", $realtime, ba, Act_b0, Act_b2);
631 
            end
632 
 
633 
            // Activate bank 0
634 
            if (ba === 2'b00 && Pc_b0 === 1'b1) begin
635 
                // Debug Message
636 
                if (Debug) begin
637 
                    //$display ("%m : at time %t ACT  : bank = 0 Row = %d", $realtime, addr);
638 
                    $display ("Time = %t : OPERATION = ACT   : bank = 0 Row = 'h%h", $realtime, addr);
639 
                end
640 
 
641 
                // Self exit to ACTIVE
642 
                if ($realtime - SELF_chk < tXSR) begin
643 
                    $display ("Time = %t : ERROR : tXSR violation(SREFX to ACT0)", $realtime);
644 
                end
645 
 
646 
                // DPDXN to Precharge
647 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
648 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT0)", $realtime);
649 
                end
650 
 
651 
                // ACTIVE to ACTIVE command period
652 
                if ($realtime - RC_chk0 < tRC) begin
653 
                    //$display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $realtime);
654 
                    $display ("Time = %t : ERROR : tRC violation (ACT0 to ACT0) ", $realtime);
655 
                end
656 
 
657 
                // Precharge to Activate bank 0
658 
                if ($realtime - RP_chk0 < tRP) begin
659 
                    //$display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $realtime);
660 
                    $display ("Time = %t : ERROR : tRP violation (PRECHARGE0 to PRECHARGE0) ", $realtime);
661 
                end
662 
 
663 
                // Record variables
664 
                Act_b0 = 1'b1;
665 
                Pc_b0 = 1'b0;
666 
                B0_row_addr = addr [no_of_addr - 1 : 0];
667 
                RAS_chk0 = $realtime;
668 
                RC_chk0 = $realtime;
669 
                RCD_chk0 = $realtime;
670 
            end
671 
 
672 
            // Activate bank 1
673 
            if (ba === 2'b01 && Pc_b1 === 1'b1) begin
674 
                // Debug Message
675 
                if (Debug) begin
676 
                    //$display ("%m : at time %t ACT  : bank = 1 Row = %d", $realtime, addr);
677 
                    $display ("Time = %t : OPERATION = ACT   : bank = 1 Row = 'h%h", $realtime, addr);
678 
                end
679 
 
680 
                // DPDXN to Precharge
681 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
682 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT1)", $realtime);
683 
                end
684 
 
685 
                // Self exit to ACTIVE
686 
                if ($realtime - SELF_chk < tXSR) begin
687 
                    $display ("Time = %t : ERROR : tXSR violation(SREFX to ACT1)", $realtime);
688 
                end
689 
 
690 
                // ACTIVE to ACTIVE command period
691 
                if ($realtime - RC_chk1 < tRC) begin
692 
                    //$display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $realtime);
693 
                    $display ("Time = %t : ERROR : tRC violation (ACT1 to ACT1) ", $realtime);
694 
                end
695 
 
696 
                // Precharge to Activate bank 1
697 
                if ($realtime - RP_chk1 < tRP) begin
698 
                    //$display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $realtime);
699 
                    $display ("Time = %t : ERROR : tRP violation (PRECHARGE1 to PRECHARGE1) ", $realtime);
700 
                end
701 
 
702 
                // Record variables
703 
                Act_b1 = 1'b1;
704 
                Pc_b1 = 1'b0;
705 
                B1_row_addr = addr [no_of_addr - 1 : 0];
706 
                RAS_chk1 = $realtime;
707 
                RC_chk1 = $realtime;
708 
                RCD_chk1 = $realtime;
709 
            end
710 
 
711 
            // Activate bank 2
712 
            if (ba === 2'b10 && Pc_b2 === 1'b1) begin
713 
                // Debug Message
714 
                if (Debug) begin
715 
                    //$display ("%m : at time %t ACT  : bank = 2 Row = %d", $realtime, addr);
716 
                    $display ("Time = %t : OPERATION = ACT   : bank = 2 Row = 'h%h", $realtime, addr);
717 
                end
718 
 
719 
                // DPDXN to Precharge
720 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
721 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT2)", $realtime);
722 
                end
723 
 
724 
                // Self exit to ACTIVE
725 
                if ($realtime - SELF_chk < tXSR) begin
726 
                    $display ("Time = %t : ERROR : tXSR violation(SREFX to ACT2)", $realtime);
727 
                end
728 
 
729 
                // ACTIVE to ACTIVE command period
730 
                if ($realtime - RC_chk2 < tRC) begin
731 
                    //$display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $realtime);
732 
                    $display ("Time = %t : ERROR : tRC violation (ACT2 to ACT2) ", $realtime);
733 
                end
734 
 
735 
                // Precharge to Activate bank 2
736 
                if ($realtime - RP_chk2 < tRP) begin
737 
                    //$display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $realtime);
738 
                    $display ("Time = %t : ERROR : tRP violation (PRECHARGE2 to PRECHARGE2) ", $realtime);
739 
                end
740 
 
741 
                // Record variables
742 
                Act_b2 = 1'b1;
743 
                Pc_b2 = 1'b0;
744 
                B2_row_addr = addr [no_of_addr - 1 : 0];
745 
                RAS_chk2 = $realtime;
746 
                RC_chk2 = $realtime;
747 
                RCD_chk2 = $realtime;
748 
            end
749 
 
750 
            // Activate bank 3
751 
            if (ba === 2'b11 && Pc_b3 === 1'b1) begin
752 
                // Debug Message
753 
                if (Debug) begin
754 
                    //$display ("%m : at time %t ACT  : bank = 3 Row = %d", $realtime, addr);
755 
                    $display ("Time = %t : OPERATION = ACT   : bank = 3 Row = 'h%h", $realtime, addr);
756 
                end
757 
 
758 
                // DPDXN to Precharge
759 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
760 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to ACT3)", $realtime);
761 
                end
762 
 
763 
                // Self exit to ACTIVE
764 
                if ($realtime - SELF_chk < tXSR) begin
765 
                    $display ("Time = %t : ERROR : tXSR violation(SREFX to ACT3)", $realtime);
766 
                end
767 
 
768 
                // ACTIVE to ACTIVE command period
769 
                if ($realtime - RC_chk3 < tRC) begin
770 
                    //$display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $realtime);
771 
                    $display ("Time = %t : ERROR : tRC violation (ACT1 to ACT3) ", $realtime);
772 
                end
773 
 
774 
                // Precharge to Activate bank 3
775 
                if ($realtime - RP_chk3 < tRP) begin
776 
                    //$display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $realtime);
777 
                    $display ("Time = %t : ERROR : tRP violation (PRECHARGE3 to PRECHARGE3) ", $realtime);
778 
                end
779 
 
780 
                // Record variables
781 
                Act_b3 = 1'b1;
782 
                Pc_b3 = 1'b0;
783 
                B3_row_addr = addr [no_of_addr - 1 : 0];
784 
                RAS_chk3 = $realtime;
785 
                RC_chk3 = $realtime;
786 
                RCD_chk3 = $realtime;
787 
            end
788 
 
789 
            // Active other bank to Active bank A
790 
            if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b00)) begin
791 
                //$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
792 
                  $display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT0) ", $realtime);
793 
            end
794 
 
795 
            // Active other bank to Active bank B
796 
            if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b01)) begin
797 
                //$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
798 
                  $display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT1) ", $realtime);
799 
            end
800 
 
801 
            // Active other bank to Active bank C
802 
            if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b10)) begin
803 
                //$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
804 
                  $display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT2) ", $realtime);
805 
            end
806 
 
807 
            // Active other bank to Active bank D
808 
            if ((Prev_bank != ba) && ($realtime - RRD_chk < tRRD) && (ba === 2'b11)) begin
809 
                //$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $realtime, ba);
810 
                  $display ("Time = %t : ERROR : tRRD violation(ACT Others to ACT3) ", $realtime);
811 
            end
812 
 
813 
            // Auto Refresh to Activate
814 
            if ($realtime - RFC_chk < tRFC) begin
815 
                //$display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $realtime, ba);
816 
                $display ("Time = %t : ERROR : tRFC violation(AREF to ACT)", $realtime);
817 
            end
818 
 
819 
            // Load Mode Register to Active
820 
            if (MRD_chk < tMRD ) begin
821 
                //$display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $realtime, ba);
822 
                $display ("Time = %t : ERROR : tMRD violation(MRS to ACT)", $realtime);
823 
            end
824 
 
825 
            // Record variables for checking violation
826 
            RRD_chk = $realtime;
827 
            Prev_bank = ba;
828 
        end
829 
 
830 
        // Precharge Block
831 
        if (Prech_enable == 1'b1) begin
832 
            // Load Mode Register to Precharge
833 
            if ($realtime - MRD_chk < tMRD) begin
834 
                //$display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $realtime);
835 
                $display ("Time = %t : ERROR : tMRD violation(MRS to PRECHARGE)", $realtime);
836 
            end
837 
 
838 
            //Precharge bank 0
839 
 
840 
            if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b00)) && Act_b0 === 1'b1) begin
841 
                Act_b0 = 1'b0;
842 
                Pc_b0 = 1'b1;
843 
                RP_chk0 = $realtime;
844 
 
845 
                if (Debug) begin
846 
                    //$display ("%m : at time %t ACT  : bank = 0 Row = %d", $realtime, addr);
847 
                    $display ("Time = %t : OPERATION = PCHG  : bank = 0 ", $realtime);
848 
                end
849 
 
850 
                // DPDXN to Precharge
851 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
852 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE0)", $realtime);
853 
                end
854 
 
855 
                // Activate to Precharge
856 
                if ($realtime - RAS_chk0 < tRAS) begin
857 
                    //$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
858 
                    $display ("Time = %t : ERROR : tRAS violation(ACT0 to PRECHARGE0)", $realtime);
859 
                end
860 
 
861 
                // tWR violation check for write
862 
                if ($realtime - WR_chkm0 < tDPLm) begin
863 
                    //$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
864 
                    $display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE0)", $realtime);
865 
                end
866 
            end
867 
 
868 
            // Precharge bank 1
869 
 
870 
            if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b01)) && Act_b1 === 1'b1) begin
871 
                Act_b1 = 1'b0;
872 
                Pc_b1 = 1'b1;
873 
                RP_chk1 = $realtime;
874 
 
875 
                if (Debug) begin
876 
                    //$display ("%m : at time %t ACT  : bank = 1 Row = %d", $realtime, addr);
877 
                    $display ("Time = %t : OPERATION = PCHG  : bank = 1 ", $realtime);
878 
                end
879 
 
880 
                // DPDXN to Precharge
881 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
882 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE1)", $realtime);
883 
                end
884 
 
885 
                // Activate to Precharge
886 
                if ($realtime - RAS_chk1 < tRAS) begin
887 
                    //$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
888 
                    $display ("Time = %t : ERROR : tRAS violation(ACT1 to PRECHARGE1)", $realtime);
889 
                end
890 
 
891 
                // tWR violation check for write
892 
                if ($realtime - WR_chkm1 < tDPLm) begin
893 
                    //$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
894 
                    $display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE1)", $realtime);
895 
                end
896 
            end
897 
 
898 
            // Precharge bank 2
899 
 
900 
            if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b10)) && Act_b2 === 1'b1) begin
901 
                Act_b2 = 1'b0;
902 
                Pc_b2 = 1'b1;
903 
                RP_chk2 = $realtime;
904 
 
905 
                if (Debug) begin
906 
                    //$display ("%m : at time %t ACT  : bank = 2 Row = %d", $realtime, addr);
907 
                    $display ("Time = %t : OPERATION = PCHG  : bank = 2 ", $realtime);
908 
                end
909 
 
910 
                // DPDXN to Precharge
911 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
912 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE2)", $realtime);
913 
                end
914 
 
915 
                // Activate to Precharge
916 
                if ($realtime - RAS_chk2 < tRAS) begin
917 
                    //$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
918 
                    $display ("Time = %t : ERROR : tRAS violation(ACT2 to PRECHARGE2)", $realtime);
919 
                end
920 
 
921 
                // tWR violation check for write
922 
                if ($realtime - WR_chkm2 < tDPLm) begin
923 
                    //$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
924 
                    $display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE2)", $realtime);
925 
                end
926 
            end
927 
 
928 
            // Precharge bank 3
929 
 
930 
            if ((addr[10] === 1'b1 || (addr[10] === 1'b0 && ba === 2'b11)) && Act_b3 === 1'b1) begin
931 
                Act_b3 = 1'b0;
932 
                Pc_b3 = 1'b1;
933 
                RP_chk3 = $realtime;
934 
 
935 
                if (Debug) begin
936 
                    //$display ("%m : at time %t ACT  : bank = 3 Row = %d", $realtime, addr);
937 
                    $display ("Time = %t : OPERATION = PCHG  : bank = 3 ", $realtime);
938 
                end
939 
 
940 
                // DPDXN to Precharge
941 
                if (($realtime - DPDN_chk < tDPDX) && (dpdn_check_start)) begin
942 
                    $display ("Time = %t : ERROR : Pwrup violation(DPDX to PRECHARGE3)", $realtime);
943 
                end
944 
 
945 
                // Activate to Precharge
946 
                if ($realtime - RAS_chk3 < tRAS) begin
947 
                    //$display ("%m : at time %t ERROR: tRAS violation during Precharge", $realtime);
948 
                    $display ("Time = %t : ERROR : tRAS violation(ACT3 to PRECHARGE3)", $realtime);
949 
                end
950 
 
951 
                // tWR violation check for write
952 
                if ($realtime - WR_chkm3 < tDPLm) begin
953 
                    //$display ("%m : at time %t ERROR: tWR violation during Precharge", $realtime);
954 
                    $display ("Time = %t : ERROR : tDPL violation(LAST DATA to PRECHARGE3)", $realtime);
955 
                end
956 
            end
957 
 
958 
 
959 
            // Terminate a Write Immediately (if same bank or all banks)
960 
            if (Data_in_enable === 1'b1 && (bank === ba || addr[10] === 1'b1)) begin
961 
                Data_in_enable = 1'b0;
962 
            end
963 
 
964 
            // Precharge Command Pipeline for Read
965 
            if (Cas_latency_3 === 1'b1) begin
966 
                Command[2] = `PRECH;
967 
                bank_precharge[2] = ba;
968 
                A10_precharge[2] = addr[10];
969 
            end else if (Cas_latency_2 === 1'b1) begin
970 
                Command[1] = `PRECH;
971 
                bank_precharge[1] = ba;
972 
                A10_precharge[1] = addr[10];
973 
            end
974 
        end
975 
 
976 
        // Burst terminate
977 
        if (Burst_term === 1'b1) begin
978 
            // Terminate a Write Immediately
979 
            if (Data_in_enable == 1'b1) begin
980 
                Data_in_enable = 1'b0;
981 
            end
982 
 
983 
            // Terminate a Read Depend on CAS Latency
984 
            if (Cas_latency_3 === 1'b1) begin
985 
                Command[2] = `BST;
986 
            end else if (Cas_latency_2 == 1'b1) begin
987 
                Command[1] = `BST;
988 
            end
989 
 
990 
            // Display debug message
991 
            if (Debug) begin
992 
                //$display ("%m : at time %t BST  : Burst Terminate",$realtime);
993 
                  $display ("Time = %t : OPERATION = BST   : Burst Stop", $realtime);
994 
            end
995 
        end
996 
 
997 
        // Read, Write, Column Latch
998 
        if (Read_enable === 1'b1) begin
999 
 
1000 
            Read_cmd_received = 1'b1;
1001 
            Read_cmd_received_cke = 1'b1;
1002 
            //Read_cmd_count = 0;
1003 
            Count_at_Read = Read_cmd_count;
1004 
            Read_cmd_count_cke = 0;
1005 
            Write_cmd_received_cke = 1'b0;
1006 
 
1007 
            // Check to see if bank is open (ACT)
1008 
            if ((ba == 2'b00 && Pc_b0 == 1'b1) || (ba == 2'b01 && Pc_b1 == 1'b1) ||
1009 
                (ba == 2'b10 && Pc_b2 == 1'b1) || (ba == 2'b11 && Pc_b3 == 1'b1)) begin
1010 
                //$display("%m : at time %t ERROR: bank is not Activated for Read", $realtime);
1011 
                  $display ("Time = %t : ERROR : bank is not Activated for Read", $realtime);
1012 
            end
1013 
 
1014 
            // Activate to Read or Write
1015 
            if ((ba == 2'b00) && ($realtime - RCD_chk0 < tRCD) ||
1016 
                (ba == 2'b01) && ($realtime - RCD_chk1 < tRCD) ||
1017 
                (ba == 2'b10) && ($realtime - RCD_chk2 < tRCD) ||
1018 
                (ba == 2'b11) && ($realtime - RCD_chk3 < tRCD)) begin
1019 
                //$display("%m : at time %t ERROR: tRCD violation during Read", $realtime);
1020 
                  $display ("Time = %t : ERROR : tRCD violation(ACT to READ)", $realtime);
1021 
            end
1022 
 
1023 
            // CAS Latency pipeline
1024 
            if (Cas_latency_3 == 1'b1) begin
1025 
                Command[2] = `READ;
1026 
                Col_addr[2] = addr;
1027 
                bank_addr[2] = ba;
1028 
            end else if (Cas_latency_2 == 1'b1) begin
1029 
                Command[1] = `READ;
1030 
                Col_addr[1] = addr;
1031 
                bank_addr[1] = ba;
1032 
            end
1033 
 
1034 
            // Read interrupt Write (terminate Write immediately)
1035 
            if (Data_in_enable == 1'b1) begin
1036 
                Data_in_enable = 1'b0;
1037 
 
1038 
                // Interrupting a Write with Autoprecharge
1039 
                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
1040 
                    RW_interrupt_write[RW_interrupt_bank] = 1'b1;
1041 
                    RW_interrupt_counter[RW_interrupt_bank] = 0;
1042 
 
1043 
                    // Display debug message
1044 
                    if (Debug) begin
1045 
                        //$display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $realtime);
1046 
                        $display ("Time = %t : OPERATION = Read interrupt Write with Autoprecharge", $realtime);
1047 
                    end
1048 
                end
1049 
            end
1050 
 
1051 
            // Read with Auto Precharge
1052 
            if (addr[10] == 1'b1) begin
1053 
                Auto_precharge[ba] = 1'b1;
1054 
                Count_precharge[ba] = 0;
1055 
                RW_interrupt_bank = ba;
1056 
                Read_precharge[ba] = 1'b1;
1057 
            end
1058 
        end
1059 
 
1060 
        // Write Command
1061 
        if (Write_enable == 1'b1) begin
1062 
 
1063 
            RIW_violate=1'b0;
1064 
            if ((Pre_Dout_Drive_Flag == 1'b1) || (Dout_Drive_Flag == 1'b1)) begin
1065 
                  $display ("Time = %t : ERROR : Read and Write Data collision", $realtime);
1066 
            end
1067 
            else if ((Data_out_enable == 1'b1) && (&(dqm_save[1]) != 1'b1)) begin
1068 
                  $display ("Time = %t : ERROR : Read and Write Data collision", $realtime);
1069 
            end
1070 
 
1071 
 
1072 
            Write_cmd_received_cke=1'b1;
1073 
            Read_cmd_received=1'b0;
1074 
            Read_cmd_received_cke=1'b0;
1075 
            Write_cmd_count_cke=1'b0;
1076 
 
1077 
            // Activate to Write
1078 
            if ((ba == 2'b00 && Pc_b0 == 1'b1) || (ba == 2'b01 && Pc_b1 == 1'b1) ||
1079 
                (ba == 2'b10 && Pc_b2 == 1'b1) || (ba == 2'b11 && Pc_b3 == 1'b1)) begin
1080 
                //$display("%m : at time %t ERROR: bank is not Activated for Write", $realtime);
1081 
                  $display ("Time = %t : ERROR : bank is not Activated for Write", $realtime);
1082 
            end
1083 
 
1084 
            if ((ba == 2'b00) && ($realtime - RCD_chk0 < tRCD)) begin
1085 
                  $display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT0 to WRITE)", $realtime, RCD_chk0,$realtime-RCD_chk0);
1086 
            end
1087 
            if ((ba == 2'b01) && ($realtime - RCD_chk1 < tRCD)) begin
1088 
                  $display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT1 to WRITE)", $realtime, RCD_chk1,$realtime-RCD_chk1);
1089 
            end
1090 
            if ((ba == 2'b10) && ($realtime - RCD_chk2 < tRCD)) begin
1091 
                  $display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT2 to WRITE)", $realtime, RCD_chk2,$realtime-RCD_chk2);
1092 
            end
1093 
            if ((ba == 2'b11) && ($realtime - RCD_chk3 < tRCD)) begin
1094 
                  $display ("Time = %t : ERROR = %t, %t: tRCD violation(ACT3 to WRITE)", $realtime, RCD_chk3,$realtime-RCD_chk3);
1095 
            end
1096 
 
1097 
 
1098 
            // Latch Write command, bank, and Column
1099 
            Command[0] = `WRITE;
1100 
            Command[1] = `NOP;
1101 
            Col_addr[0] = addr;
1102 
            bank_addr[0] = ba;
1103 
 
1104 
            // Write interrupt Write (terminate Write immediately)
1105 
            if (Data_in_enable == 1'b1) begin
1106 
                Data_in_enable = 1'b0;
1107 
 
1108 
                // Interrupting a Write with Autoprecharge
1109 
                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
1110 
                    RW_interrupt_write[RW_interrupt_bank] = 1'b1;
1111 
 
1112 
                    // Display debug message
1113 
                    if (Debug) begin
1114 
                        //$display ("%m : at time %t NOTE : Read bank %d interrupt Write bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
1115 
                        $display ("Time = %t : OPERATION = Write bank %d interrupt Write bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
1116 
 
1117 
                    end
1118 
                end
1119 
            end
1120 
 
1121 
            // Write interrupt Read (terminate Read immediately)
1122 
            if (Data_out_enable == 1'b1) begin
1123 
                Data_out_enable = 1'b0;
1124 
 
1125 
                // Interrupting a Read with Autoprecharge
1126 
                if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
1127 
                    RW_interrupt_read[RW_interrupt_bank] = 1'b1;
1128 
 
1129 
                    // Display debug message
1130 
                    if (Debug) begin
1131 
                        //$display ("%m : at time %t NOTE : Write bank %d interrupt Read bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
1132 
                        $display ("Time = %t : OPERATION = Write bank %d interrupt Read bank %d with Autoprecharge", $realtime, ba, RW_interrupt_bank);
1133 
                    end
1134 
                end
1135 
            end
1136 
 
1137 
            // Write with Auto Precharge
1138 
            if (addr[10] == 1'b1) begin
1139 
                Auto_precharge[ba] = 1'b1;
1140 
                Count_precharge[ba] = 0;
1141 
                RW_interrupt_bank = ba;
1142 
                Write_precharge[ba] = 1'b1;
1143 
            end
1144 
        end
1145 
 
1146 
        /*
1147 
            Write with Auto Precharge Calculation
1148 
                The device start internal precharge when:
1149 
                    1.  Meet minimum tRAS requirement
1150 
                and 2.  tWR cycle(s) after last valid data
1151 
                 or 3.  Interrupt by a Read or Write (with or without Auto Precharge)
1152 
 
1153 
            Note: Model is starting the internal precharge 1 cycle after they meet all the
1154 
                  requirement but tRP will be compensate for the time after the 1 cycle.
1155 
        */
1156 
        if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
1157 
            if ((($realtime - RAS_chk0 >= tRAS) &&                                                          // Case 1
1158 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) ||   // Case 2
1159 
                 (Burst_length_2 == 1'b1                              && Count_precharge [0] >= 2) ||
1160 
                 (Burst_length_4 == 1'b1                              && Count_precharge [0] >= 4) ||
1161 
                 (Burst_length_8 == 1'b1                              && Count_precharge [0] >= 8))) ||
1162 
                 (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin                 // Case 3
1163 
                    Auto_precharge[0] = 1'b0;
1164 
                    Write_precharge[0] = 1'b0;
1165 
                    RW_interrupt_write[0] = 1'b0;
1166 
                    Pc_b0 = 1'b1;
1167 
                    Act_b0 = 1'b0;
1168 
                    RP_chk0 = $realtime + tDPLa;
1169 
                    if (Debug) begin
1170 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 0", $realtime);
1171 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 0", $realtime+tDPLa);
1172 
                    end
1173 
            end
1174 
        end
1175 
        if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
1176 
            if ((($realtime - RAS_chk1 >= tRAS) &&                                                          // Case 1
1177 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) ||   // Case 2
1178 
                 (Burst_length_2 == 1'b1                              && Count_precharge [1] >= 2) ||
1179 
                 (Burst_length_4 == 1'b1                              && Count_precharge [1] >= 4) ||
1180 
                 (Burst_length_8 == 1'b1                              && Count_precharge [1] >= 8))) ||
1181 
                 (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin                 // Case 3
1182 
                    Auto_precharge[1] = 1'b0;
1183 
                    Write_precharge[1] = 1'b0;
1184 
                    RW_interrupt_write[1] = 1'b0;
1185 
                    Pc_b1 = 1'b1;
1186 
                    Act_b1 = 1'b0;
1187 
                    RP_chk1 = $realtime + tDPLa;
1188 
                    if (Debug) begin
1189 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 1", $realtime);
1190 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 1", $realtime+tDPLa);
1191 
                    end
1192 
            end
1193 
        end
1194 
        if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
1195 
            if ((($realtime - RAS_chk2 >= tRAS) &&                                                          // Case 1
1196 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) ||   // Case 2
1197 
                 (Burst_length_2 == 1'b1                              && Count_precharge [2] >= 2) ||
1198 
                 (Burst_length_4 == 1'b1                              && Count_precharge [2] >= 4) ||
1199 
                 (Burst_length_8 == 1'b1                              && Count_precharge [2] >= 8))) ||
1200 
                 (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin                 // Case 3
1201 
                    Auto_precharge[2] = 1'b0;
1202 
                    Write_precharge[2] = 1'b0;
1203 
                    RW_interrupt_write[2] = 1'b0;
1204 
                    Pc_b2 = 1'b1;
1205 
                    Act_b2 = 1'b0;
1206 
                    RP_chk2 = $realtime + tDPLa;
1207 
                    if (Debug) begin
1208 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 2", $realtime);
1209 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 2", $realtime+tDPLa);
1210 
                    end
1211 
            end
1212 
        end
1213 
        if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
1214 
            if ((($realtime - RAS_chk3 >= tRAS) &&                                                          // Case 1
1215 
               (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) ||   // Case 2
1216 
                 (Burst_length_2 == 1'b1                              && Count_precharge [3] >= 2) ||
1217 
                 (Burst_length_4 == 1'b1                              && Count_precharge [3] >= 4) ||
1218 
                 (Burst_length_8 == 1'b1                              && Count_precharge [3] >= 8))) ||
1219 
                 (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin                 // Case 3
1220 
                    Auto_precharge[3] = 1'b0;
1221 
                    Write_precharge[3] = 1'b0;
1222 
                    RW_interrupt_write[3] = 1'b0;
1223 
                    Pc_b3 = 1'b1;
1224 
                    Act_b3 = 1'b0;
1225 
                    RP_chk3 = $realtime + tDPLa;
1226 
                    if (Debug) begin
1227 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 3", $realtime);
1228 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 3", $realtime+tDPLa);
1229 
                    end
1230 
            end
1231 
        end
1232 
 
1233 
        //  Read with Auto Precharge Calculation
1234 
        //      The device start internal precharge:
1235 
        //          1.  Meet minimum tRAS requirement
1236 
        //      and 2.  CAS Latency - 1 cycles before last burst
1237 
        //       or 3.  Interrupt by a Read or Write (with or without AutoPrecharge)
1238 
        if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
1239 
            if ((($realtime - RAS_chk0 >= tRAS) &&                                                      // Case 1
1240 
                ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) ||                             // Case 2
1241 
                 (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
1242 
                 (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
1243 
                 (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
1244 
                 (RW_interrupt_read[0] == 1'b1)) begin                                              // Case 3
1245 
                    Pc_b0 = 1'b1;
1246 
                    Act_b0 = 1'b0;
1247 
                    RP_chk0 = $realtime;
1248 
                    Auto_precharge[0] = 1'b0;
1249 
                    Read_precharge[0] = 1'b0;
1250 
                    RW_interrupt_read[0] = 1'b0;
1251 
                    if (Debug) begin
1252 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 0", $realtime);
1253 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 0", $realtime);
1254 
                    end
1255 
            end
1256 
        end
1257 
        if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
1258 
            if ((($realtime - RAS_chk1 >= tRAS) &&
1259 
                ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
1260 
                 (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
1261 
                 (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
1262 
                 (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
1263 
                 (RW_interrupt_read[1] == 1'b1)) begin
1264 
                    Pc_b1 = 1'b1;
1265 
                    Act_b1 = 1'b0;
1266 
                    RP_chk1 = $realtime;
1267 
                    Auto_precharge[1] = 1'b0;
1268 
                    Read_precharge[1] = 1'b0;
1269 
                    RW_interrupt_read[1] = 1'b0;
1270 
                    if (Debug) begin
1271 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 1", $realtime);
1272 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 1", $realtime);
1273 
                    end
1274 
            end
1275 
        end
1276 
        if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
1277 
            if ((($realtime - RAS_chk2 >= tRAS) &&
1278 
                ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
1279 
                 (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
1280 
                 (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
1281 
                 (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
1282 
                 (RW_interrupt_read[2] == 1'b1)) begin
1283 
                    Pc_b2 = 1'b1;
1284 
                    Act_b2 = 1'b0;
1285 
                    RP_chk2 = $realtime;
1286 
                    Auto_precharge[2] = 1'b0;
1287 
                    Read_precharge[2] = 1'b0;
1288 
                    RW_interrupt_read[2] = 1'b0;
1289 
                    if (Debug) begin
1290 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 2", $realtime);
1291 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 2", $realtime);
1292 
                    end
1293 
            end
1294 
        end
1295 
        if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
1296 
            if ((($realtime - RAS_chk3 >= tRAS) &&
1297 
                ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
1298 
                 (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
1299 
                 (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
1300 
                 (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
1301 
                 (RW_interrupt_read[3] == 1'b1)) begin
1302 
                    Pc_b3 = 1'b1;
1303 
                    Act_b3 = 1'b0;
1304 
                    RP_chk3 = $realtime;
1305 
                    Auto_precharge[3] = 1'b0;
1306 
                    Read_precharge[3] = 1'b0;
1307 
                    RW_interrupt_read[3] = 1'b0;
1308 
                    if (Debug) begin
1309 
                        //$display ("%m : at time %t NOTE : Start Internal Auto Precharge for bank 3", $realtime);
1310 
                        $display ("Time = %t : OPERATION = Start Internal Auto Precharge for bank 3", $realtime);
1311 
                    end
1312 
            end
1313 
        end
1314 
 
1315 
        // CKE Function
1316 
        if (cke === 1'b0) begin
1317 
          if (Sref_enable === 1'b1) begin
1318 
            state_self = 1'b1;
1319 
            if (Debug) begin
1320 
                $display ("Time = %t : OPERATION = SREF  : Self Refresh", $realtime);
1321 
                if (EMode_reg[2:0]==3'b000) $display ("         Refresh Full Bank");
1322 
 
1323 
                if (EMode_reg[2:0]==3'b001) begin
1324 
                     $display ("                Refresh Only TWO Bank");
1325 
                     abbank_init;
1326 
                end
1327 
 
1328 
                if (EMode_reg[2:0]==3'b010) begin
1329 
                     $display ("                Refresh Only One Bank(BANK A)");
1330 
                     bbank_init;
1331 
                end
1332 
                if (EMode_reg[2:0]==3'b101) begin
1333 
                     $display ("                Refresh Only half of one Bank(BANK A, A10=0)");
1334 
                     half_init;
1335 
                end
1336 
                if (EMode_reg[2:0]==3'b110) begin
1337 
                     $display ("                Refresh Only Quarter of one Bank(BANK A, A10=0)");
1338 
                     quat_init;
1339 
                end
1340 
            end
1341 
 
1342 
            // Precharge to Auto Refresh
1343 
            if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
1344 
                ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP))
1345 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE to SREF)", $realtime);
1346 
 
1347 
            // Precharge to Refresh
1348 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0)
1349 
                $display ("Time = %t : ERROR : All banks must be Precharged before SREF", $realtime);
1350 
 
1351 
            // Load Mode Register to Self Refresh
1352 
            if (MRD_chk < tMRD)
1353 
                $display ("Time = %t : ERROR : tMRD violation(MRS to SREF)", $realtime);
1354 
 
1355 
          end else if (Deep_pwrdn == 1'b1) begin
1356 
            state_dpdn = 1'b1;
1357 
            dpdn_check_start = 1'b1;
1358 
            Act_b0 = 0; Act_b1 = 0; Act_b2 = 0; Act_b3 = 0;
1359 
            Pc_b0 = 1; Pc_b1 = 1; Pc_b2 = 1; Pc_b3 = 1;
1360 
            mem_init;
1361 
            if (Debug) $display ("Time = %t : OPERATION = DPDN  : Deep Powerdown", $realtime);
1362 
 
1363 
            // Precharge to Auto Refresh
1364 
            if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
1365 
                ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP))
1366 
                $display ("Time = %t : ERROR : tRP violation(PRECHARGE to DPDN)", $realtime);
1367 
 
1368 
            // Precharge to Refresh
1369 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0)
1370 
                $display ("Time = %t : ERROR : All banks must be Precharged before DPDN", $realtime);
1371 
 
1372 
          end else if (act_pwrdn == 1'b1) begin
1373 
            state_act_pwrdn = 1'b1;
1374 
            if (Debug) $display ("Time = %t : OPERATION = APDN  : Active Power down", $realtime);
1375 
          end else if (pch_pwrdn == 1'b1) begin
1376 
            state_pre_pwrdn = 1'b1;
1377 
            if (Debug) $display ("Time = %t : OPERATION = PPDN  : Precharge Power down", $realtime);
1378 
          end else if (clk_suspend_write == 1'b1) begin
1379 
            if (Debug) $display ("Time = %t : OPERATION = CKSW   : Clock Suspend during Write", $realtime);
1380 
          end else if (clk_suspend_read == 1'b1) begin
1381 
            if (Debug) $display ("Time = %t : OPERATION = CKSR   : Clock Suspend during Read", $realtime);
1382 
          end
1383 
        end
1384 
 
1385 
        // Internal Precharge or Bst
1386 
        if (Command[0] == `PRECH) begin                         // Precharge terminate a read with same bank or all banks
1387 
            if (bank_precharge[0] == bank || A10_precharge[0] == 1'b1) begin
1388 
                if (Data_out_enable == 1'b1) begin
1389 
                    Data_out_enable = 1'b0;
1390 
                end
1391 
            end
1392 
        end else if (Command[0] == `BST) begin                  // BST terminate a read to current bank
1393 
            if (Data_out_enable == 1'b1) begin
1394 
                Data_out_enable = 1'b0;
1395 
            end
1396 
        end
1397 
 
1398 
        if (Data_out_enable == 1'b0) begin
1399 
            dq_reg <= #tOH {no_of_data{1'bz}};
1400 
            Dout_Drive_Flag <= #tOH 1'b0;
1401 
        end
1402 
 
1403 
        // Detect Read or Write command
1404 
        if (Command[0] == `READ) begin
1405 
            bank = bank_addr[0];
1406 
            Col = Col_addr[0];
1407 
            Col_brst = Col_addr[0];
1408 
            case (bank_addr[0])
1409 
                2'b00 : Row = B0_row_addr;
1410 
                2'b01 : Row = B1_row_addr;
1411 
                2'b10 : Row = B2_row_addr;
1412 
                2'b11 : Row = B3_row_addr;
1413 
 
1414 
            endcase
1415 
            Burst_counter = 0;
1416 
            Data_in_enable = 1'b0;
1417 
            Data_out_enable = 1'b1;
1418 
        end else if (Command[0] == `WRITE) begin
1419 
            bank = bank_addr[0];
1420 
            Col = Col_addr[0];
1421 
            Col_brst = Col_addr[0];
1422 
            case (bank_addr[0])
1423 
                2'b00 : Row = B0_row_addr;
1424 
                2'b01 : Row = B1_row_addr;
1425 
                2'b10 : Row = B2_row_addr;
1426 
                2'b11 : Row = B3_row_addr;
1427 
            endcase
1428 
            Burst_counter = 0;
1429 
            Data_in_enable = 1'b1;
1430 
            Data_out_enable = 1'b0;
1431 
        end
1432 
 
1433 
        // DQ buffer (Driver/Receiver)
1434 
        if (Data_in_enable == 1'b1) begin                                   // Writing Data to Memory
1435 
            // Array buffer
1436 
            case (bank)
1437 
                2'b00 : dq_dqm = bank0 [{Row, Col}];
1438 
                2'b01 : dq_dqm = bank1 [{Row, Col}];
1439 
                2'b10 : dq_dqm = bank2 [{Row, Col}];
1440 
                2'b11 : dq_dqm = bank3 [{Row, Col}];
1441 
            endcase
1442 
 
1443 
            // dqm operation
1444 
            if (dqm[0] == 1'b0) begin
1445 
                dq_dqm [ 7 : 0] = dq [ 7 : 0 ] & dq [ 7 : 0 ];
1446 
            end
1447 
            if (dqm[1] == 1'b0) begin
1448 
                dq_dqm [15 : 8] = dq [15 : 8] & dq [15 : 8];
1449 
            end
1450 
 
1451 
 
1452 
 
1453 
            // Write to memory
1454 
            case (bank)
1455 
                2'b00 : bank0 [{Row, Col}] = dq_dqm;
1456 
                2'b01 : bank1 [{Row, Col}] = dq_dqm;
1457 
                2'b10 : bank2 [{Row, Col}] = dq_dqm;
1458 
                2'b11 : bank3 [{Row, Col}] = dq_dqm;
1459 
            endcase
1460 
 
1461 
            // Display debug message
1462 
            if (dqm !== 2'b11) begin
1463 
                // Record tWR for manual precharge
1464 
                if (bank == 2'b00) WR_chkm0 = $realtime;
1465 
                if (bank == 2'b01) WR_chkm1 = $realtime;
1466 
                if (bank == 2'b10) WR_chkm2 = $realtime;
1467 
                if (bank == 2'b11) WR_chkm3 = $realtime;
1468 
 
1469 
                if (Debug) begin
1470 
                    //$display("%m : at time %t WRITE: bank = %d Row = %d, Col = %d, Data = %d", $realtime, bank, Row, Col, dq_dqm);
1471 
                    $display ("Time = %t : OPERATION = WRITE : bank = %d Row = 'h%h, Col = 'h%h, Data = 'h%h", $realtime, bank, Row, Col, dq_dqm);
1472 
                end
1473 
            end else begin
1474 
                if (Debug) begin
1475 
                    //$display("%m : at time %t WRITE: bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1476 
                    $display ("Time = %t : OPERATION = WRITE : bank = %d Row = 'h%h, Col = 'h%h, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1477 
                end
1478 
            end
1479 
 
1480 
            // Advance burst counter subroutine
1481 
 
1482 
                if(Cas_latency_2 == 1) begin
1483 
 
1484 
                         #tHZ2 Burst_decode;
1485 
 
1486 
                end else if(Cas_latency_3 == 1) begin
1487 
 
1488 
                         #tHZ3 Burst_decode;
1489 
 
1490 
                end
1491 
 
1492 
 
1493 
        end else if (Data_out_enable == 1'b1) begin                         // Reading Data from Memory
1494 
            // Array buffer
1495 
            case (bank)
1496 
                2'b00 : dq_dqm = bank0[{Row, Col}];
1497 
                2'b01 : dq_dqm = bank1[{Row, Col}];
1498 
                2'b10 : dq_dqm = bank2[{Row, Col}];
1499 
                2'b11 : dq_dqm = bank3[{Row, Col}];
1500 
            endcase
1501 
 
1502 
 
1503 
            // dqm operation
1504 
            if (dqm_reg0 [0] == 1'b1) begin
1505 
                dq_dqm [ 7 : 0] = 8'bz;
1506 
            end
1507 
            if (dqm_reg0 [1] == 1'b1) begin
1508 
                dq_dqm [15 : 8] = 8'bz;
1509 
            end
1510 
 
1511 
            if(Cas_latency_2 ==1) begin
1512 
 
1513 
            // Display debug message
1514 
            if ( &(dqm_reg0) != 1'b1) begin
1515 
                dq_reg = #tAC2 dq_dqm;
1516 
                Dout_Drive_Flag = 1'b1;
1517 
                if (Debug) begin
1518 
                    //$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = %d", $realtime, bank, Row, Col, dq_reg);
1519 
                    $display ("Time = %t : OPERATION = READ  : bank = %d Row = 'h%h, Col = 'h%h, Data = 'h%h", $realtime, bank, Row, Col, dq_reg);
1520 
                end
1521 
            end else begin
1522 
                dq_reg = #tHZ2 {no_of_data{1'bz}};
1523 
                Dout_Drive_Flag = 1'b0;
1524 
                if (Debug) begin
1525 
                    //$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1526 
                    $display ("Time = %t : OPERATION = READ  : bank = %d Row = 'h%h, Col = 'h%h, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1527 
 
1528 
                end
1529 
            end
1530 
 
1531 
            end else if(Cas_latency_3 ==1) begin
1532 
 
1533 
            // Display debug message
1534 
            if ( &(dqm_reg0) != 1'b1) begin
1535 
                dq_reg = #tAC3 dq_dqm;
1536 
                Dout_Drive_Flag = 1'b1;
1537 
                if (Debug) begin
1538 
                    //$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = %d", $realtime, bank, Row, Col, dq_reg);
1539 
                    $display ("Time = %t : OPERATION = READ  : bank = %d Row = 'h%h, Col = 'h%h, Data = 'h%h", $realtime, bank, Row, Col, dq_reg);
1540 
                end
1541 
            end else begin
1542 
                dq_reg = #tHZ3 {no_of_data{1'bz}};
1543 
                Dout_Drive_Flag = 1'b0;
1544 
                if (Debug) begin
1545 
                    //$display("%m : at time %t READ : bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1546 
                    $display ("Time = %t : OPERATION = READ  : bank = %d Row = 'h%h, Col = 'h%h, Data = Hi-Z due to DQM", $realtime, bank, Row, Col);
1547 
 
1548 
                end
1549 
            end
1550 
 
1551 
           end
1552 
 
1553 
            // Advance burst counter subroutine
1554 
            Burst_decode;
1555 
        end
1556 
    end
1557 
 
1558 
    // Burst counter decode
1559 
    task Burst_decode;
1560 
        begin
1561 
            // Advance Burst Counter
1562 
            Burst_counter = Burst_counter + 1;
1563 
 
1564 
            // Burst Type
1565 
            if (Mode_reg[3] == 1'b0) begin                                  // Sequential Burst
1566 
                Col_temp = Col + 1;
1567 
            end else if (Mode_reg[3] == 1'b1) begin                         // Interleaved Burst
1568 
                Col_temp[2] =  Burst_counter[2] ^  Col_brst[2];
1569 
                Col_temp[1] =  Burst_counter[1] ^  Col_brst[1];
1570 
                Col_temp[0] =  Burst_counter[0] ^  Col_brst[0];
1571 
            end
1572 
 
1573 
            // Burst Length
1574 
            if (Burst_length_2) begin                                       // Burst Length = 2
1575 
                Col [0] = Col_temp [0];
1576 
            end else if (Burst_length_4) begin                              // Burst Length = 4
1577 
                Col [1 : 0] = Col_temp [1 : 0];
1578 
            end else if (Burst_length_8) begin                              // Burst Length = 8
1579 
                Col [2 : 0] = Col_temp [2 : 0];
1580 
            end else begin                                                  // Burst Length = FULL
1581 
                Col = Col_temp;
1582 
            end
1583 
 
1584 
            // Burst Read Single Write
1585 
            if (Write_burst_mode == 1'b1) begin
1586 
                Data_in_enable = 1'b0;
1587 
            end
1588 
 
1589 
            // Data Counter
1590 
            if (Burst_length_1 == 1'b1) begin
1591 
                if (Burst_counter >= 1) begin
1592 
                    Data_in_enable = 1'b0;
1593 
                    Data_out_enable = 1'b0;
1594 
                end
1595 
            end else if (Burst_length_2 == 1'b1) begin
1596 
                if (Burst_counter >= 2) begin
1597 
                    Data_in_enable = 1'b0;
1598 
                    Data_out_enable = 1'b0;
1599 
                end
1600 
            end else if (Burst_length_4 == 1'b1) begin
1601 
                if (Burst_counter >= 4) begin
1602 
                    Data_in_enable = 1'b0;
1603 
                    Data_out_enable = 1'b0;
1604 
                end
1605 
            end else if (Burst_length_8 == 1'b1) begin
1606 
                if (Burst_counter >= 8) begin
1607 
                    Data_in_enable = 1'b0;
1608 
                    Data_out_enable = 1'b0;
1609 
                end
1610 
            end
1611 
        end
1612 
    endtask
1613 
 
1614 
    task mem_init;
1615 
        begin
1616 
          for (ccc=0;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
1617 
          begin
1618 
              bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1619 
              bank1[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1620 
              bank2[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1621 
              bank3[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1622 
              //bank0[ccc]=16'b1111_1111_1111_1111;
1623 
              //bank1[ccc]=16'b1111_1111_1111_1111;
1624 
          end
1625 
        end
1626 
    endtask
1627 
 
1628 
    task abbank_init;
1629 
        begin
1630 
          for (ccc=0;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
1631 
          begin
1632 
              bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1633 
              bank1[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1634 
          end
1635 
        end
1636 
    endtask
1637 
 
1638 
 
1639 
    task bbank_init;
1640 
        begin
1641 
          for (ccc=0;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
1642 
          begin
1643 
              bank1[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1644 
          end
1645 
        end
1646 
    endtask
1647 
 
1648 
    task half_init;
1649 
        begin
1650 
          bbank_init;
1651 
          for (ccc='b0100_0000_0000_0000_0000;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
1652 
          begin
1653 
              bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1654 
          end
1655 
        end
1656 
    endtask
1657 
 
1658 
    task quat_init;
1659 
        begin
1660 
          bbank_init;
1661 
          for (ccc='b0010_0000_0000_0000_0000;ccc<'b1000_0000_0000_0000_0000;ccc=ccc+1)
1662 
          begin
1663 
              bank0[ccc]=32'bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
1664 
          end
1665 
        end
1666 
    endtask
1667 
`endprotect
1668 
 
1669 
    // Timing Parameters
1670 
    specify
1671 
        specparam
1672 
          `ifdef S50
1673 
            tAH  =  1.0,                                        // addr, ba Hold Time
1674 
            tAS  =  1.5,                                        // addr, ba Setup Time
1675 
            tCH  =  2.5,                                        // Clock High-Level Width
1676 
            tCL  =  2.5,                                        // Clock Low-Level Width
1677 
            tCK  =  5.0,                                        // Clock Cycle Time
1678 
            tDH  =  1.0,                                        // Data-in Hold Time
1679 
            tDS  =  1.5,                                        // Data-in Setup Time
1680 
            tCKH =  1.0,                                        // CKE Hold  Time
1681 
            tCKS =  1.5,                                        // CKE Setup Time
1682 
            tCMH =  1.0,                                        // CSB, RASB, CASB, WEB, DQMB Hold  Time
1683 
            tCMS =  1.5;                                        // CSB, RASB, CASB, WEB, DQMB Setup Time
1684 
          `endif
1685 
 
1686 
          `ifdef S60
1687 
            tAH  =  1.0,                                        // addr, ba Hold Time
1688 
            tAS  =  1.5,                                        // addr, ba Setup Time
1689 
            tCH  =  2.5,                                        // Clock High-Level Width
1690 
            tCL  =  2.5,                                        // Clock Low-Level Width
1691 
            tCK  =  6.0,                                        // Clock Cycle Time
1692 
            tDH  =  1.0,                                        // Data-in Hold Time
1693 
            tDS  =  1.5,                                        // Data-in Setup Time
1694 
            tCKH =  1.0,                                        // CKE Hold  Time
1695 
            tCKS =  1.5,                                        // CKE Setup Time
1696 
            tCMH =  1.0,                                        // CSB, RASB, CASB, WEB, DQMB Hold  Time
1697 
            tCMS =  1.5;                                        // CSB, RASB, CASB, WEB, DQMB Setup Time
1698 
          `endif
1699 
 
1700 
          `ifdef S75
1701 
            tAH  =  1.0,                                        // addr, ba Hold Time
1702 
            tAS  =  2.0,                                        // addr, ba Setup Time
1703 
            tCH  =  2.5,                                        // Clock High-Level Width
1704 
            tCL  =  2.5,                                        // Clock Low-Level Width
1705 
            tCK  =  7.5,                                        // Clock Cycle Time
1706 
            tDH  =  1.0,                                        // Data-in Hold Time
1707 
            tDS  =  2.0,                                        // Data-in Setup Time
1708 
            tCKH =  1.0,                                        // CKE Hold  Time
1709 
            tCKS =  2.0,                                        // CKE Setup Time
1710 
            tCMH =  1.0,                                        // CSB, RASB, CASB, WEB, DQMB Hold  Time
1711 
            tCMS =  2.0;                                        // CSB, RASB, CASB, WEB, DQMB Setup Time
1712 
          `endif
1713 
 
1714 
 
1715 
        $width    (posedge clk,           tCH);
1716 
        $width    (negedge clk,           tCL);
1717 
        $period   (negedge clk,           tCK);
1718 
        $period   (posedge clk,           tCK);
1719 
        $setuphold(posedge clk,    cke,   tCKS, tCKH);
1720 
        $setuphold(posedge clk,    csb,  tCMS, tCMH);
1721 
        $setuphold(posedge clk,    casb, tCMS, tCMH);
1722 
        $setuphold(posedge clk,    rasb, tCMS, tCMH);
1723 
        $setuphold(posedge clk,    web,  tCMS, tCMH);
1724 
        $setuphold(posedge clk,    addr,  tAS,  tAH);
1725 
        $setuphold(posedge clk,    ba,    tAS,  tAH);
1726 
        $setuphold(posedge clk,    dqm,   tCMS, tCMH);
1727 
        $setuphold(posedge dq_chk, dq,    tDS,  tDH);
1728 
    endspecify
1729 
 
1730 
 
1731 
endmodule

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