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[/] [sdram_16bit/] [trunk/] [testbench/] [simulation.svh] - Blame information for rev 2

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Line No. Rev Author Line
1 2 ultra_embe
`timescale 1ns/1ps
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//-----------------------------------------------------------------
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// assert_task
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//-----------------------------------------------------------------
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task automatic assert_task(input v, string file, int line, input string s);
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begin
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    if (!v)
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    begin
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        $display("ASSERT: %s:%0d - %s", file, line, s);
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        $finish(1);
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    end
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end
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endtask
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//-----------------------------------------------------------------
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// ASSERT
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//-----------------------------------------------------------------
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`define ASSERT(v)    assert_task(v, `__FILE__, `__LINE__, `"v`")
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//-----------------------------------------------------------------
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// ASSERT_ALWAYS
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//-----------------------------------------------------------------
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`define ASSERT_ALWAYS(condition) \
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    generate \
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        if(1) \
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        begin \
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        wire test = condition; \
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        always @(test)\
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         `ASSERT(condition); \
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        end \
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    endgenerate
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//-----------------------------------------------------------------
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// TB_TIMEOUT
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//-----------------------------------------------------------------
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`define TB_TIMEOUT(CLK, RST, VALID, TIMEOUT) \
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    integer v_timeout_cycles;   \
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                            \
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    always @(posedge ``RST or posedge ``CLK)   \
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    if (``RST)   \
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        v_timeout_cycles <= 0; \
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    else  \
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    begin  \
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        if (``VALID)  \
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        begin  \
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            v_timeout_cycles <= 0; \
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        end  \
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        else  \
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        begin  \
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            v_timeout_cycles <= v_timeout_cycles + 1; \
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            `ASSERT(v_timeout_cycles < ``TIMEOUT);  \
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        end  \
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    end
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//-----------------------------------------------------------------
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// CLOCK_GEN
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//-----------------------------------------------------------------
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`define CLOCK_GEN(NAME, CYCLE)     \
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    reg ``NAME;      \
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    initial \
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    begin \
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       ``NAME <= 0; \
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       forever # (``CYCLE / 2) ``NAME = ~``NAME; \
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    end
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//-----------------------------------------------------------------
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// RESET_GEN
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//-----------------------------------------------------------------
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`define RESET_GEN(NAME, DELAY)     \
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    reg ``NAME;      \
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    initial \
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    begin \
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       ``NAME <= 1; \
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       # ``DELAY    \
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       ``NAME <= 0; \
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    end
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//-----------------------------------------------------------------
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// TB_VCD
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//-----------------------------------------------------------------
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`define TB_VCD(TOP, NAME)     \
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    initial \
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    begin \
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       $dumpfile(``NAME);  \
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       $dumpvars(0,``TOP); \
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    end
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//-----------------------------------------------------------------
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// TB_RUN_FOR
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//-----------------------------------------------------------------
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`define TB_RUN_FOR(TIME)    initial #``TIME $finish;

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