OpenCores
URL https://opencores.org/ocsvn/softavrcore/softavrcore/trunk

Subversion Repositories softavrcore

[/] [softavrcore/] [trunk/] [build/] [crt0.s] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 apal
;=============================================================================;
2
 
3
.set    PINB,   0x16
4
 
5
.set    VECTOR_SIZE,    2
6
.set    VECTOR_WIDTH,   2
7
 
8
.set    VECTOR_NUM,     1<<VECTOR_WIDTH
9
.set    AVR_REG_SIZE,   0x0020
10
.set    AVR_IO_SIZE,    0x0040
11
.set    RAM_SIZE,       0x0200
12
 
13
;=============================================================================;
14
 
15
.set    _RAMEND_ADDR,   AVR_REG_SIZE + AVR_IO_SIZE + RAM_SIZE
16
.set    _VECTORS_SIZE,  VECTOR_SIZE * VECTOR_NUM
17
.set    __stack_pointer, _RAMEND_ADDR - 1
18
.set    AVR_STACK_POINTER_LO_ADDR, 0x3d
19
.set    AVR_STACK_POINTER_HI_ADDR, 0x3e
20
.set    AVR_SREG_ADDR, 0x3f
21
 
22
.macro  XJMP name
23
        .if (VECTOR_SIZE == 2)
24
        rjmp    \name
25
        .elseif (VECTOR_SIZE == 4)
26
        jmp     \name
27
        .else
28
        nop
29
        .endif
30
.endm
31
 
32
.macro  XCALL name
33
        .if (VECTOR_SIZE == 2)
34
        rcall   \name
35
        .elseif (VECTOR_SIZE == 4)
36
        call    \name
37
        .else
38
        nop
39
        .endif
40
.endm
41
 
42
.macro  vector name
43
        .if (. - __vectors < _VECTORS_SIZE)
44
        .weak   \name
45
        .set    \name, __bad_interrupt
46
        XJMP    \name
47
        .endif
48
.endm
49
 
50
.section .vectors,"ax",@progbits
51
        .global __vectors
52
        .func   __vectors
53
 
54
__vectors:
55
 
56
        ;in     r16, PINB
57
        ;ldi    r16, 0xC0
58
        ;out    0x04, r16
59
        ;rjmp   __vectors
60
 
61
        XJMP    __init
62
        vector  __vector_1
63
        vector  __vector_2
64
        vector  __vector_3
65
        vector  __vector_4
66
        vector  __vector_5
67
        vector  __vector_6
68
        vector  __vector_7
69
        vector  __vector_8
70
        vector  __vector_9
71
        vector  __vector_10
72
        vector  __vector_11
73
        vector  __vector_12
74
        vector  __vector_13
75
        vector  __vector_14
76
        vector  __vector_15
77
        .endfunc
78
 
79
        .global __bad_interrupt
80
        .func   __bad_interrupt
81
__bad_interrupt:
82
        .weak   __vector_default
83
        .set    __vector_default, __bad_interrupt
84
        rjmp    __vector_default
85
        .endfunc
86
 
87
__init:
88
 
89
        eor     r1, r1
90
        out     AVR_SREG_ADDR, r1
91
        ldi     r28,lo8(__stack_pointer)
92
        out     AVR_STACK_POINTER_LO_ADDR, r28
93
        ldi     r29,hi8(__stack_pointer)
94
        out     AVR_STACK_POINTER_HI_ADDR, r29
95
 
96
.section .init9,"ax",@progbits
97
 
98
        XCALL   main
99
        XJMP    exit

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.