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[/] [softavrcore/] [trunk/] [peripherals/] [avr_io_timer.v] - Blame information for rev 2

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1 2 apal
/*****************************************************************************/
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/* avr_io_timer.v                                                            */
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/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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/* (c) 2019-2020; Andras Pal <apal@szofi.net>                                */
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/*****************************************************************************/
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module avr_io_timer
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 (      input clk,
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        input rst,
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        input io_re,
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        input io_we,
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        input [1:0] io_a,
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        output [7:0] io_do,
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        input [7:0] io_di,
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        output  irq
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 );
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reg [15:0] TCNT;
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reg [7:0]  TTMP;
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reg [7:0]  TCR;
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reg [11:0]       prescaler;
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reg [3:0]        pre_prev;
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reg             overflow;
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wire [7:0] TSR = { overflow, 7'b0000000 };
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assign irq = TSR[7] & TCR[7];
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/* I/O read: */
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reg [7:0] io_do_data;
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always @(*) begin
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        casex (io_a)
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                2'b00: io_do_data = TCNT[7:0];
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                2'b01: io_do_data = TTMP[7:0];
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                2'b10: io_do_data = TCR;
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                2'b11: io_do_data = TSR;
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        endcase
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end
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assign io_do = io_re ? io_do_data : 8'b00000000;
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always @(posedge clk) begin
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        if (io_we & ~io_re) begin
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                if ( io_a==2'b01 ) TTMP <= io_di;
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                if ( io_a==2'b10 ) TCR  <= io_di;
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        end else if ( io_re ) begin
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                if ( io_a==2'b00 )
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                        TTMP <= TCNT[15:8];
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        end
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end
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wire tcnt_write = io_we & (io_a==2'b00);
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wire tcr_write  = io_we & (io_a==2'b10);
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/* Note: the interrupt is cleared when the overflow flag is reset: therefore, any write
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into the TNCT _or_ the TCR register would clear the interrupt: */
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wire o = overflow & (~tcr_write);
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reg increment;
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always @(*) begin
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        casex (TCR[1:0])
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                2'b00: increment = 1;
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                2'b01: increment = (~prescaler[ 3])&pre_prev[0];
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                2'b10: increment = (~prescaler[ 7])&pre_prev[1];
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                2'b11: increment = (~prescaler[11])&pre_prev[2];
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        endcase
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end
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always @(posedge clk) begin
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        if ( ! tcnt_write ) begin
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                prescaler <= prescaler + 1;
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                pre_prev  <= { prescaler[11], prescaler[7], prescaler[3] };
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                { overflow, TCNT } <= { o, 16'd0 } | ( { o, TCNT } + increment );
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        end else begin
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                TCNT <= { TTMP, io_di };
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                prescaler <= 0;
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                overflow <= 0;
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        end
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end
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/*****************************************************************************/
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/* Debug section starts here */
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/* end of debug section */
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/*****************************************************************************/
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endmodule
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/*****************************************************************************/

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