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[/] [softavrcore/] [trunk/] [peripherals/] [avr_systick.v] - Blame information for rev 2

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1 2 apal
/*****************************************************************************/
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/* avr_systick.v                                                             */
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/*****************************************************************************/
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/* Registers                                                                 */
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/*      STCNTL  r       BASE + 0x00             { CNT[7:0] }                 */
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/*      STCNTH  r       BASE + 0x01             { OVERFLOW, CNT[14:8] }      */
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/*      STLOADL r+w     BASE + 0x02             { CLOAD[7:0] }               */
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/*      STLOADH r+w     BASE + 0x03             { IENABLE, CLOAD[14:8] }     */
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/*****************************************************************************/
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module avr_systick
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 (      input clk,
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        input rst,
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        input   io_re,
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        input   io_we,
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        input   [1:0] io_a,
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        output  [7:0] io_do,
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        input   [7:0] io_di,
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        output  irq
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 );
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reg IENABLE;
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reg CLOAD[14:0];
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reg OVERFLOW;
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reg [14:0] CNT;
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reg [6:0] CTMP;
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assign irq = IENABLE & OVERFLOW;
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/* I/O read: */
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reg [7:0] io_do_data;
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always @(*) begin
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        casex (io_a)
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                2'b00: io_do_data = CNT[7:0];
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                2'b01: io_do_data = { OVERFLOW, CTMP };
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                2'b10: io_do_data = CLOAD[7:0];
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                2'b11: io_do_data = { IENABLE, CLOAD[14:8] } ;
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        endcase
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end
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assign io_do = io_re ? io_do_data : 8'b00000000;
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wire reset_overflow_bit = (io_we & (io_a[1]==0));
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always @(posedge clk) begin
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        if (io_we & ~io_re) begin
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                if ( io_a==2'b10 ) begin
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                        CLOAD[7:0]  <= io_di;
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                end else if ( io_a==2'b11 ) begin
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                        { IENABLE, CLOAD[14:8] } <= io_di;
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                end
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        end else if ( io_re ) begin
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                if ( io_a==2'b00 )
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                        CTMP <= CNT[15:8];
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        end
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end
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always @(posedge clk) begin
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        if ( reset_overflow_bit ) begin
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                OVERFLOW <= 0;
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        end else if ( CNT[14:0]==0 ) begin
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                CNT <= CLOAD;
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                OVERFLOW <= 1;
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        end else begin
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                CNT <= CNT - 1;
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        end
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end
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/*****************************************************************************/
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/* Debug section starts here */
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/* end of debug section */
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/*****************************************************************************/
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endmodule
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/*****************************************************************************/

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