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[/] [softavrcore/] [trunk/] [synth/] [top.v] - Blame information for rev 2

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1 2 apal
`include "avr_core.v"
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`include "avr_io_out.v"
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`include "avr_io_uart.v"
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`include "avr_io_timer.v"
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`include "main.v"
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//`include "flash.v"
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`include "ram.v"
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//`include "avr_io_spi.v"
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/*****************************************************************************/
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module priority_encoder ( input [3:0] irq_lines , output iflag, output reg [1:0] ivect );
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//reg [1:0] ivect;
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always @(*) begin
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        if (irq_lines[0])       ivect = 0;
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        else if (irq_lines[1])  ivect = 1;
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        else if (irq_lines[2])  ivect = 2;
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        else if (irq_lines[3])  ivect = 3;
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        else                    ivect = 0;
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end
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assign  iflag = |irq_lines;
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endmodule
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/*****************************************************************************/
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module top
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 (      input   hwclk,
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        output  [7:0] led,
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        input   ftdi_rx,
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        output  ftdi_tx,
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        inout   pin_scl0,
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        inout   pin_sda0
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 );
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//assign sseg4 = 13'b1_1111_1111_1111;
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wire            clk;
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parameter       pmem_width = 10;
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parameter       dmem_width = 9;
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wire                    pmem_ce;
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wire [pmem_width-1:0]    pmem_a;
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wire [15:0]              pmem_d;
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wire                    dmem_re;
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wire                    dmem_we;
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wire [dmem_width-1:0]    dmem_a;
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wire [7:0]               dmem_di;
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wire [7:0]               dmem_do;
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wire                    io_re;
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wire                    io_we;
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wire [5:0]               io_a;
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wire [7:0]               io_do;
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SB_PLL40_CORE
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 #(     .FEEDBACK_PATH("SIMPLE"),
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        .PLLOUT_SELECT("GENCLK"),
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        .ENABLE_ICEGATE("0"),
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        .DIVR(4'b0000),
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        .DIVF(7'b0111111),
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        .DIVQ(3'b100),
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        .FILTER_RANGE(3'b001)
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  )
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pll
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 (      .RESETB(1'b1),
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        .BYPASS(1'b1),
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        .EXTFEEDBACK(1'b0),
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        .LATCHINPUTVALUE(1'b0),
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        .DYNAMICDELAY(8'b00000000),
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        .REFERENCECLK(hwclk),
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        .SDI(1'b0),
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        .SCLK(1'b0),
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        .PLLOUTGLOBAL(clk)
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 );
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//reg [1:0] clkcnt;
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//always @(posedge hwclk) clkcnt <= clkcnt + 1;
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//assign clk = clkcnt[1];
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//BUFG clkcrt ( .I(clkcnt[1]), .O(clk) );
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/*****************************************************************************/
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ram      core0_ram ( clk, dmem_re, dmem_we, dmem_a, dmem_di, dmem_do );
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defparam core0_ram.ram_width = dmem_width;
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flash    core0_flash ( clk, pmem_ce,pmem_a, pmem_d );
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//defparam core0_flash.flash_width = pmem_width;
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/*****************************************************************************/
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wor [7:0] io_di;
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`define TIMER0
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`ifdef TIMER0
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wire timer0_io_select = (io_a[5:2] == 4'b0010);
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wire timer0_io_re = timer0_io_select & io_re;
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wire timer0_io_we = timer0_io_select & io_we;
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wire timer0_irq;
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avr_io_timer timer0
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 (      clk, 1'b0,
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        timer0_io_re, timer0_io_we, io_a[1:0], io_di, io_do,
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        timer0_irq
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 );
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`else
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wire timer0_irq = 0;
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`endif
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/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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`define PORT0
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`ifdef PORT0
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wire port0_io_select = (io_a[5:0] == 6'b000100);
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wire port0_io_re = (port0_io_select ? io_re : 1'b0);
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wire port0_io_we = (port0_io_select ? io_we : 1'b0);
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wire [7:0] port0_out;
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avr_io_out port0
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 (      clk, 1'b0,
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        port0_io_re, port0_io_we, io_di, io_do,
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        port0_out
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 );
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assign led = port0_out;
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`else
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assign led = 8'b00000000;
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`endif
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/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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`define UART0
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`ifdef UART0
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wire uart0_io_select = (io_a[5:2] == 4'b0000);
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wire uart0_io_re = (uart0_io_select ? io_re : 1'b0);
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wire uart0_io_we = (uart0_io_select ? io_we : 1'b0);
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wire uart0_txd;
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wire uart0_rxd;
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wire [2:0] uart0_irq;
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assign ftdi_tx = uart0_txd;
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assign uart0_rxd = ftdi_rx;
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avr_io_uart uart0
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 (      clk, 1'b0,
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        uart0_io_re, uart0_io_we, io_a[1:0], io_di, io_do,
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        uart0_txd, uart0_rxd,
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        uart0_irq
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 );
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`else
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assign ftdi_tx = ftdi_rx;
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wire [2:0] uart0_irq;
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assign uart0_irq = 3'b000;
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`endif
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/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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// `define SPI0
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`ifdef SPI0
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wire spi0_io_select = (io_a[5:2] == 4'b0100);
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wire spi0_io_re = (spi0_io_select ? io_re : 1'b0);
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wire spi0_io_we = (spi0_io_select ? io_we : 1'b0);
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wire spi0_enable;
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wire spi0_master;
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wire spi0_master_out;
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wire spi0_master_in;
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wire spi0_master_clk;
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wire spi0_master_select;
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wire spi0_slave_out;
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`define ASYNC_SPI_SAMPLING
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`ifdef ASYNC_SPI_SAMPLING
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assign mosi = spi0_master_out;
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assign spi0_master_in = miso;
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assign sck = spi0_master_clk;
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assign nss = ~spi0_master_select;
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`else
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reg     mosi, spi0_master_in, sck, nss;
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always @(posedge clk) begin
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        mosi <= spi0_master_out;
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        spi0_master_in <= miso;
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        sck <= spi0_master_clk;
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        nss <= ~spi0_master_select;
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end
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`endif
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avr_io_spi spi0
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 (      clk, 1'b0,
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        spi0_io_re, spi0_io_we, io_a[1:0], io_di, io_do,
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        spi0_enable, spi0_master,
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        spi0_master_clk, spi0_master_out, spi0_master_in, spi0_master_select,
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        1'b0, 1'b0, spi0_slave_out, 1'b0
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 );
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`else
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//assign sck = 1'b0;
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//assign mosi = 1'b0;
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//assign nss = 1'b1;
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`endif
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/*****************************************************************************/
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wire iflag;
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wire [1:0] ivect;
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priority_encoder irq0 ( { uart0_irq[2], 1'b0, timer0_irq, 1'b0 }, iflag, ivect );
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avr_core core0
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 (      clk, 1'b0,
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        pmem_ce, pmem_a, pmem_d,
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        dmem_re, dmem_we, dmem_a, dmem_di, dmem_do,
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        io_re, io_we, io_a, io_di, io_do,
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        iflag, ivect
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 );
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defparam core0.pmem_width = pmem_width;
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defparam core0.dmem_width = dmem_width;
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defparam core0.interrupt  = 1;
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defparam core0.intr_width = 2;
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endmodule
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