OpenCores
URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [bench/] [vhdl/] [streamtest_tb.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jorisvr
--
2
-- Test bench for spwstream.
3
--
4
-- Tests:
5
--  * one spwstream instance with SpaceWire signals looped back to itself
6
--  * sending of bytes, packets and time codes through the SpaceWire link
7
--  * handling of link disabling and link disconnection
8
--
9
-- This test bench is intended to test the buffering logic in spwstream.
10
-- It does not thoroughly verify behaviour of the receiver, transmitter,
11
-- signal patterns etc. Please use spwlink_tb.vhd to test those aspects.
12
--
13
 
14
library ieee;
15
use ieee.std_logic_1164.all;
16
use ieee.numeric_std.all;
17
use std.textio.all;
18
use work.spwpkg.all;
19
 
20
entity streamtest_tb is
21
end entity;
22
 
23
architecture tb_arch of streamtest_tb is
24
 
25
    -- Parameters.
26
    constant sys_clock_freq: real   := 20.0e6;
27
 
28
    component streamtest is
29
        generic (
30
            sysfreq:    real;
31 3 jorisvr
            txclkfreq:  real;
32 2 jorisvr
            tickdiv:    integer range 12 to 24 := 20;
33
            rximpl:     spw_implementation_type := impl_generic;
34
            rxchunk:    integer range 1 to 4 := 1;
35
            tximpl:     spw_implementation_type := impl_generic;
36
            rxfifosize_bits: integer range 6 to 14 := 11;
37
            txfifosize_bits: integer range 2 to 14 := 11 );
38
        port (
39
            clk:        in  std_logic;
40
            rxclk:      in  std_logic;
41
            txclk:      in  std_logic;
42
            rst:        in  std_logic;
43
            linkstart:  in  std_logic;
44
            autostart:  in  std_logic;
45
            linkdisable: in std_logic;
46
            senddata:   in  std_logic;
47
            sendtick:   in  std_logic;
48
            txdivcnt:   in  std_logic_vector(7 downto 0);
49
            linkstarted: out std_logic;
50
            linkconnecting: out std_logic;
51
            linkrun:    out std_logic;
52
            linkerror:  out std_logic;
53
            gotdata:    out std_logic;
54
            dataerror:  out std_logic;
55
            tickerror:  out std_logic;
56
            spw_di:     in  std_logic;
57
            spw_si:     in  std_logic;
58
            spw_do:     out std_logic;
59
            spw_so:     out std_logic );
60
    end component;
61
 
62
    signal sys_clock_enable: std_logic := '0';
63
    signal sysclk:      std_logic := '0';
64
    signal s_loopback:  std_logic := '0';
65
    signal s_nreceived: integer := 0;
66
 
67
    signal s_rst:       std_logic := '1';
68
    signal s_linkstart: std_logic;
69
    signal s_autostart: std_logic;
70
    signal s_linkdisable: std_logic;
71
    signal s_divcnt:    std_logic_vector(7 downto 0);
72
    signal s_linkrun:   std_logic;
73
    signal s_linkerror: std_logic;
74
    signal s_gotdata:   std_logic;
75
    signal s_dataerror: std_logic;
76
    signal s_tickerror: std_logic;
77
    signal s_spwdi:     std_logic;
78
    signal s_spwsi:     std_logic;
79
    signal s_spwdo:     std_logic;
80
    signal s_spwso:     std_logic;
81
 
82
begin
83
 
84
    -- streamtest instance
85
    streamtest_inst: streamtest
86
        generic map (
87
            sysfreq     => sys_clock_freq,
88 3 jorisvr
            txclkfreq   => sys_clock_freq,
89 2 jorisvr
            tickdiv     => 16,
90
            rximpl      => impl_generic,
91
            rxchunk     => 1,
92
            tximpl      => impl_generic,
93
            rxfifosize_bits => 9,
94
            txfifosize_bits => 8 )
95
        port map (
96
            clk         => sysclk,
97
            rxclk       => sysclk,
98
            txclk       => sysclk,
99
            rst         => s_rst,
100
            linkstart   => s_linkstart,
101
            autostart   => s_autostart,
102
            linkdisable => s_linkdisable,
103
            senddata    => '1',
104
            sendtick    => '1',
105
            txdivcnt    => s_divcnt,
106
            linkstarted => open,
107
            linkconnecting => open,
108
            linkrun     => s_linkrun,
109
            linkerror   => s_linkerror,
110
            gotdata     => s_gotdata,
111
            dataerror   => s_dataerror,
112
            tickerror   => s_tickerror,
113
            spw_di      => s_spwdi,
114
            spw_si      => s_spwsi,
115
            spw_do      => s_spwdo,
116
            spw_so      => s_spwso );
117
 
118
    -- Conditional loopback of SpaceWire signals.
119
    s_spwdi <= s_spwdo when (s_loopback = '1') else '0';
120
    s_spwsi <= s_spwso when (s_loopback = '1') else '0';
121
 
122
    -- Generate system clock.
123
    process is
124
    begin
125
        if sys_clock_enable /= '1' then
126
            wait until sys_clock_enable = '1';
127
        end if;
128
        sysclk  <= '1';
129
        wait for (0.5 sec) / sys_clock_freq;
130
        sysclk  <= '0';
131
        wait for (0.5 sec) / sys_clock_freq;
132
    end process;
133
 
134
    -- Verify that error indications remain off.
135
    process is
136
    begin
137
        wait on s_linkerror, s_dataerror, s_tickerror;
138
        assert s_dataerror = '0' report "Detected data error";
139
        assert s_tickerror = '0' report "Detected time code error";
140
        if s_loopback = '1' then
141
            assert s_linkerror /= '1' report "Unexpected link error";
142
        end if;
143
    end process;
144
 
145
    -- Verify that data is received regularly when the link is up.
146
    process is
147
    begin
148
        if s_linkrun = '0' or s_gotdata = '1' then
149
            wait until s_linkrun = '1' and s_gotdata = '0';
150
        end if;
151
        wait until s_gotdata = '1' or s_linkrun = '0' for 3 ms;
152
        if s_linkrun = '1' then
153
            assert s_gotdata = '1' report "Link running but no data received";
154
        end if;
155
    end process;
156
 
157
    -- Count number of received characters.
158
    process is
159
    begin
160
        wait until rising_edge(sysclk);
161
        if s_gotdata = '1' then
162
            s_nreceived <= s_nreceived + 1;
163
        end if;
164
    end process;
165
 
166
    -- Main process.
167
    process is
168
        variable vline: LINE;
169
    begin
170
        report "Starting streamtest test bench";
171
 
172
        -- Initialize.
173
        s_loopback  <= '1';
174
        s_rst       <= '1';
175
        s_linkstart <= '0';
176
        s_autostart <= '0';
177
        s_linkdisable <= '0';
178
        s_divcnt    <= "00000001";
179
        sys_clock_enable <= '1';
180
        wait for 1 us;
181
 
182
        -- Test link and data transmission.
183
        report "Testing txdivcnt = 1";
184
        s_rst       <= '0';
185
        s_linkstart <= '1';
186
        wait for 100 us;
187
        assert s_linkrun = '1' report "Link failed to start";
188
        wait for 50 ms;
189
 
190
        -- Check number of received characters.
191
        write(vline, string'("Received "));
192
        write(vline, s_nreceived);
193
        write(vline, string'(" characters in 50 ms."));
194
        writeline(output, vline);
195
        assert s_nreceived > 24000 report "Too few characters received";
196
 
197
        -- Test switching to different transmission rate.
198
        report "Testing txdivcnt = 2";
199
        s_divcnt    <= "00000010";
200
        wait for 10 ms;
201
        report "Testing txdivcnt = 3";
202
        s_divcnt    <= "00000011";
203
        wait for 10 ms;
204
 
205
        -- Disable and re-enable link.
206
        report "Testing link disable/re-enable";
207
        s_linkdisable <= '1';
208
        s_divcnt    <= "00000001";
209
        wait for 2 ms;
210
        s_linkdisable <= '0';
211
        wait for 100 us;
212
        assert s_linkrun = '1' report "Link failed to start after re-enable";
213
        wait for 10 ms;
214
 
215
        -- Cut and reconnect loopback wiring.
216
        report "Testing physical disconnect/reconnect";
217
        s_loopback  <= '0';
218
        wait for 2 ms;
219
        s_loopback  <= '1';
220
        wait for 100 us;
221
        assert s_linkrun = '1' report "Link failed to start after reconnect";
222
        wait for 10 ms;
223
        s_loopback  <= '0';
224
        wait for 2 ms;
225
        s_loopback  <= '1';
226
        wait for 100 us;
227
        assert s_linkrun = '1' report "Link failed to start after reconnect (2)";
228
        wait for 10 ms;
229
 
230
        -- Shut down.
231
        s_rst   <= '1';
232
        wait for 1 us;
233
        sys_clock_enable <= '0';
234
 
235
        write(vline, string'("Received "));
236
        write(vline, s_nreceived);
237
        write(vline, string'(" characters."));
238
        writeline(output, vline);
239
 
240
        report "Done";
241
        wait;
242
    end process;
243
 
244
end architecture tb_arch;

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.