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[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwpkg.vhd] - Blame information for rev 2

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1 2 jorisvr
--
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--  SpaceWire VHDL package
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--
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library ieee;
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use ieee.std_logic_1164.all;
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package spwpkg is
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10
 
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    -- Indicates a platform-specific implementation.
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    type spw_implementation_type is ( impl_generic, impl_fast );
13
 
14
 
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    -- Input signals to spwlink.
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    type spw_link_in_type is record
17
 
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        -- Enables automatic link start on receipt of a NULL character.
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        autostart:  std_logic;
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        -- Enables link start once the Ready state is reached.
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        -- Without either "autostart" or "linkstart", the link remains in
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        -- state Ready.
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        linkstart:  std_logic;
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        -- Do not start link (overrides "linkstart" and "autostart") and/or
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        -- disconnect the currently running link.
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        linkdis:    std_logic;
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        -- Number of bytes available in the receive buffer. Used to for
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        -- flow-control operation. At least 8 bytes must be available
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        -- initially, otherwise the link can not start. Values larger than 63
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        -- are irrelevant and may be presented as 63. The available room may
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        -- decrease by one byte due to the reception of an N-Char; in that case
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        -- the "rxroom" signal must be updated on the clock following the clock
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        -- on which "rxchar" is high. Under no other circumstances may "rxroom"
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        -- be decreased.
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        rxroom:     std_logic_vector(5 downto 0);
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        -- High for one clock cycle to request transmission of a TimeCode.
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        -- The request is registered inside spwxmit until it can be processed.
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        tick_in:    std_logic;
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        -- Control bits of the TimeCode to be sent.
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        -- Must be valid while tick_in is high.
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        ctrl_in:    std_logic_vector(1 downto 0);
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        -- Counter value of the TimeCode to be sent.
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        -- Must be valid while tick_in is high.
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        time_in:    std_logic_vector(5 downto 0);
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        -- Requests transmission of an N-Char.
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        -- Keep this signal high until confirmed by "txack".
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        txwrite:    std_logic;
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        -- Control flag to be sent with the next N-Char.
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        -- Must be valid while "txwrite" is high.
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        txflag:     std_logic;
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        -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
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        -- Must be valid while "txwrite" is high.
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        txdata:     std_logic_vector(7 downto 0);
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    end record;
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    -- Output signals from spwlink.
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    type spw_link_out_type is record
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        -- High if the link state machine is currently in state Started.
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        started:    std_logic;
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        -- High if the link state machine is currently in state Connecting.
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        connecting: std_logic;
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        -- High if the link state machine is currently in state Run.
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        running:    std_logic;
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        -- Disconnect detected in state Run. Triggers a reset and reconnect.
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        -- This indication is auto-clearing.
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        errdisc:    std_logic;
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        -- Parity error detected in state Run. Triggers a reset and reconnect.
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        -- This indication is auto-clearing.
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        errpar:     std_logic;
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        -- Invalid escape sequence detected in state Run.
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        -- Triggers a reset and reconnect; auto-clearing.
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        erresc:     std_logic;
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        -- Credit error detected. Triggers a reset and reconnect.
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        -- This indication is auto-clearing.
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        errcred:    std_logic;
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        -- High to confirm the transmission of an N-Char.
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        -- This is a Wishbone-style handshake signal. It has a combinatorial
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        -- dependency on "txwrite".
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        txack:      std_logic;
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        -- High for one clock cycle if a TimeCode was just received.
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        -- Verification of the TimeCode as described in 8.12.2 of ECSS-E-50
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        -- is not implemented; all received timecodes are reported.
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        tick_out:   std_logic;
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        -- Control bits of last received TimeCode.
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        ctrl_out:   std_logic_vector(1 downto 0);
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        -- Counter value of last received TimeCode.
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        time_out:   std_logic_vector(5 downto 0);
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        -- High for one clock cycle if an N-Char (data byte or EOP or EEP) was
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        -- just received. The data bits must be accepted immediately from
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        -- "rxflag" and "rxdata".
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        rxchar:     std_logic;
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        -- High if the received character is EOP or EEP, low if it is a data
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        -- byte. Valid when "rxchar" is high.
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        rxflag:     std_logic;
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        -- Received byte, or "00000000" for EOP or "00000001" for EEP.
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        -- Valid when "rxchar" is high.
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        rxdata:     std_logic_vector(7 downto 0);
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    end record;
124
 
125
 
126
    -- Output signals from spwrecv to spwlink.
127
    type spw_recv_out_type is record
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129
        -- High if at least one signal change was seen since enable.
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        -- Resets to low when rxen is low.
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        gotbit:     std_logic;
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133
        -- High if at least one valid NULL pattern was detected since enable.
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        -- Resets to low when rxen is low.
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        gotnull:    std_logic;
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137
        -- High for one clock cycle if an FCT token was just received.
138
        gotfct:     std_logic;
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140
        -- High for one clock cycle if a TimeCode was just received.
141
        tick_out:   std_logic;
142
 
143
        -- Control bits of last received TimeCode.
144
        ctrl_out:   std_logic_vector(1 downto 0);
145
 
146
        -- Counter value of last received TimeCode.
147
        time_out:   std_logic_vector(5 downto 0);
148
 
149
        -- High for one clock cycle if an N-Char (data byte or EOP/EEP) was just received.
150
        rxchar:     std_logic;
151
 
152
        -- High if rxchar is high and the received character is EOP or EEP.
153
        -- Low if rxchar is high and the received character is a data byte.
154
        rxflag:     std_logic;
155
 
156
        -- Received byte, or "00000000" for EOP or "00000001" for EEP.
157
        -- Valid when "rxchar" is high.
158
        rxdata:     std_logic_vector(7 downto 0);
159
 
160
        -- Disconnect detected (after a signal change was seen).
161
        -- Resets to low when rxen is low or when a signal change is seen.
162
        errdisc:    std_logic;
163
 
164
        -- Parity error detected (after a valid NULL pattern was seen).
165
        -- Sticky; resets to low when rxen is low.
166
        errpar:     std_logic;
167
 
168
        -- Escape sequence error detected (after a valid NULL pattern was seen).
169
        -- Sticky; resets to low when rxen is low.
170
        erresc:     std_logic;
171
    end record;
172
 
173
 
174
    -- Input signals to spwxmit from spwlink.
175
    type spw_xmit_in_type is record
176
 
177
        -- High to enable transmitter; low to disable and reset transmitter.
178
        txen:       std_logic;
179
 
180
        -- Indicates that only NULL characters may be transmitted.
181
        stnull:     std_logic;
182
 
183
        -- Indicates that only NULL and/or FCT characters may be transmitted.
184
        stfct:      std_logic;
185
 
186
        -- Requests transmission of an FCT character.
187
        -- Keep this signal high until confirmed by "fctack".
188
        fct_in:     std_logic;
189
 
190
        -- High for one clock cycle to request transmission of a TimeCode.
191
        -- The request is registered inside spwxmit until it can be processed.
192
        tick_in:    std_logic;
193
 
194
        -- Control bits of the TimeCode to be sent.
195
        -- Must be valid while "tick_in" is high.
196
        ctrl_in:    std_logic_vector(1 downto 0);
197
 
198
        -- Counter value of the TimeCode to be sent.
199
        -- Must be valid while "tick_in" is high.
200
        time_in:    std_logic_vector(5 downto 0);
201
 
202
        -- Request transmission of an N-Char.
203
        -- Keep this signal high until confirmed by "txack".
204
        txwrite:    std_logic;
205
 
206
        -- Control flag to be sent with the next N-Char.
207
        -- Must be valid while "txwrite" is high.
208
        txflag:     std_logic;
209
 
210
        -- Byte to send, or "00000000" for EOP or "00000001" for EEP.
211
        -- Must be valid while "txwrite" is high.
212
        txdata:     std_logic_vector(7 downto 0);
213
    end record;
214
 
215
 
216
    -- Output signals from spwxmit to spwlink.
217
    type spw_xmit_out_type is record
218
 
219
        -- High to confirm transmission on an FCT character.
220
        -- This is a Wishbone-style handshaking signal; it is combinatorially
221
        -- dependent on "fct_in".
222
        fctack:     std_logic;
223
 
224
        -- High to confirm transmission of an N-Char.
225
        -- This is a Wishbone-style handshaking signal; it is combinatorially
226
        -- dependent on both "fct_in" and "txwrite".
227
        txack:      std_logic;
228
    end record;
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230
 
231
    -- Character-stream interface
232
    component spwstream is
233
        generic (
234
            sysfreq:        real;                           -- clk freq in Hz
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            rximpl:         spw_implementation_type := impl_generic;
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            rxchunk:        integer range 1 to 4 := 1;      -- max bits per clk
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            tximpl:         spw_implementation_type := impl_generic;
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            rxfifosize_bits: integer range 6 to 14 := 11;   -- rx fifo size
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            txfifosize_bits: integer range 2 to 14 := 11    -- tx fifo size
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        );
241
        port (
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            clk:        in  std_logic;          -- system clock
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            rxclk:      in  std_logic;          -- receiver sample clock
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            txclk:      in  std_logic;          -- transmit clock
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            rst:        in  std_logic;          -- synchronous reset
246
            autostart:  in  std_logic;          -- automatic link start
247
            linkstart:  in  std_logic;          -- forced link start
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            linkdis:    in  std_logic;          -- stop link
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            txdivcnt:   in  std_logic_vector(7 downto 0);   -- tx scale factor
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            tick_in:    in  std_logic;          -- request timecode xmit
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            ctrl_in:    in  std_logic_vector(1 downto 0);
252
            time_in:    in  std_logic_vector(5 downto 0);
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            txwrite:    in  std_logic;          -- request character xmit
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            txflag:     in  std_logic;          -- control flag of tx char
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            txdata:     in  std_logic_vector(7 downto 0);
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            txrdy:      out std_logic;          -- room in tx fifo
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            txhalff:    out std_logic;          -- tx fifo half full
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            tick_out:   out std_logic;          -- timecode received
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            ctrl_out:   out std_logic_vector(1 downto 0);
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            time_out:   out std_logic_vector(5 downto 0);
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            rxvalid:    out std_logic;          -- rx fifo not empty
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            rxhalff:    out std_logic;          -- rx fifo half full
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            rxflag:     out std_logic;          -- control flag of rx char
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            rxdata:     out std_logic_vector(7 downto 0);
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            rxread:     in  std_logic;          -- accept rx character
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            started:    out std_logic;          -- link in Started state
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            connecting: out std_logic;          -- link in Connecting state
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            running:    out std_logic;          -- link in Run state
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            errdisc:    out std_logic;          -- disconnect error
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            errpar:     out std_logic;          -- parity error
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            erresc:     out std_logic;          -- escape error
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            errcred:    out std_logic;          -- credit error
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            spw_di:     in  std_logic;
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            spw_si:     in  std_logic;
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            spw_do:     out std_logic;
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            spw_so:     out std_logic
277
        );
278
    end component spwstream;
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281
    -- Link Level Interface
282
    component spwlink is
283
        generic (
284
            reset_time:      integer        -- reset time in clocks (6.4 us)
285
        );
286
        port (
287
            clk:        in  std_logic;      -- system clock
288
            rst:        in  std_logic;      -- synchronous reset (active-high)
289
            linki:      in  spw_link_in_type;
290
            linko:      out spw_link_out_type;
291
            rxen:       out std_logic;
292
            recvo:      in  spw_recv_out_type;
293
            xmiti:      out spw_xmit_in_type;
294
            xmito:      in  spw_xmit_out_type
295
        );
296
    end component spwlink;
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298
 
299
    -- Receiver
300
    component spwrecv is
301
        generic (
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            disconnect_time: integer range 1 to 255;    -- disconnect period in system clock cycles
303
            rxchunk:        integer range 1 to 4        -- nr of bits per system clock
304
        );
305
        port (
306
            clk:        in  std_logic;      -- system clock
307
            rxen:       in  std_logic;      -- receiver enabled
308
            recvo:      out spw_recv_out_type;
309
            inact:      in  std_logic;
310
            inbvalid:   in  std_logic;
311
            inbits:     in  std_logic_vector(rxchunk-1 downto 0)
312
        );
313
    end component spwrecv;
314
 
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316
    -- Transmitter (generic implementation)
317
    component spwxmit is
318
        port (
319
            clk:        in  std_logic;      -- system clock
320
            rst:        in  std_logic;      -- synchronous reset (active-high)
321
            divcnt:     in  std_logic_vector(7 downto 0);
322
            xmiti:      in  spw_xmit_in_type;
323
            xmito:      out spw_xmit_out_type;
324
            spw_do:     out std_logic;      -- tx data to SPW bus
325
            spw_so:     out std_logic       -- tx strobe to SPW bus
326
        );
327
    end component spwxmit;
328
 
329
 
330
    -- Transmitter (separate tx clock domain)
331
    component spwxmit_fast is
332
        port (
333
            clk:        in  std_logic;      -- system clock
334
            txclk:      in  std_logic;      -- transmit clock
335
            rst:        in  std_logic;      -- synchronous reset (active-high)
336
            divcnt:     in  std_logic_vector(7 downto 0);
337
            xmiti:      in  spw_xmit_in_type;
338
            xmito:      out spw_xmit_out_type;
339
            spw_do:     out std_logic;      -- tx data to SPW bus
340
            spw_so:     out std_logic       -- tx strobe to SPW bus
341
        );
342
    end component spwxmit_fast;
343
 
344
 
345
    -- Front-end for SpaceWire Receiver (generic implementation)
346
    component spwrecvfront_generic is
347
        port (
348
            clk:        in  std_logic;      -- system clock
349
            rxen:       in  std_logic;      -- high to enable receiver
350
            inact:      out std_logic;      -- high if activity on input
351
            inbvalid:   out std_logic;      -- high if inbits contains a valid received bit
352
            inbits:     out std_logic_vector(0 downto 0);   -- received bit
353
            spw_di:     in  std_logic;      -- Data In signal from SpaceWire bus
354
            spw_si:     in  std_logic       -- Strobe In signal from SpaceWire bus
355
        );
356
    end component spwrecvfront_generic;
357
 
358
 
359
    -- Front-end for SpaceWire Receiver (separate rx clock domain)
360
    component spwrecvfront_fast is
361
        generic (
362
            rxchunk:        integer range 1 to 4    -- max number of bits per system clock
363
        );
364
        port (
365
            clk:        in  std_logic;      -- system clock
366
            rxclk:      in  std_logic;      -- sample clock (DDR)
367
            rxen:       in  std_logic;      -- high to enable receiver
368
            inact:      out std_logic;      -- high if activity on input
369
            inbvalid:   out std_logic;      -- high if inbits contains a valid group of received bits
370
            inbits:     out std_logic_vector(rxchunk-1 downto 0);    -- received bits
371
            spw_di:     in  std_logic;      -- Data In signal from SpaceWire bus
372
            spw_si:     in  std_logic       -- Strobe In signal from SpaceWire bus
373
        );
374
    end component spwrecvfront_fast;
375
 
376
 
377
    -- Synchronous dual-port memory.
378
    component spwram is
379
        generic (
380
            abits:      integer;
381
            dbits:      integer );
382
        port (
383
            rclk:       in  std_logic;
384
            wclk:       in  std_logic;
385
            ren:        in  std_logic;
386
            raddr:      in  std_logic_vector(abits-1 downto 0);
387
            rdata:      out std_logic_vector(dbits-1 downto 0);
388
            wen:        in  std_logic;
389
            waddr:      in  std_logic_vector(abits-1 downto 0);
390
            wdata:      in  std_logic_vector(dbits-1 downto 0) );
391
    end component spwram;
392
 
393
end package;

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