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[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwram.vhd] - Blame information for rev 2

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1 2 jorisvr
--
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--  Synchronous dual-port RAM with separate clocks for read and write ports.
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--  The synthesizer for Xilinx Spartan-3 will infer Block RAM for this entity.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity spwram is
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    generic (
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        abits:      integer;
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        dbits:      integer );
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    port (
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        rclk:       in  std_logic;
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        wclk:       in  std_logic;
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        ren:        in  std_logic;
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        raddr:      in  std_logic_vector(abits-1 downto 0);
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        rdata:      out std_logic_vector(dbits-1 downto 0);
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        wen:        in  std_logic;
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        waddr:      in  std_logic_vector(abits-1 downto 0);
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        wdata:      in  std_logic_vector(dbits-1 downto 0) );
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end entity spwram;
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architecture spwram_arch of spwram is
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    type mem_type is array(0 to (2**abits - 1)) of
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                     std_logic_vector(dbits-1 downto 0);
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    signal s_mem:   mem_type;
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begin
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    -- read process
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    process (rclk) is
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    begin
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        if rising_edge(rclk) then
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            if ren = '1' then
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                rdata <= s_mem(to_integer(unsigned(raddr)));
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            end if;
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        end if;
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    end process;
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    -- write process
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    process (wclk) is
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    begin
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        if rising_edge(wclk) then
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            if wen = '1' then
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                s_mem(to_integer(unsigned(waddr))) <= wdata;
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            end if;
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        end if;
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    end process;
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end architecture;
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