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[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwrecvfront_fast.vhd] - Blame information for rev 2

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1 2 jorisvr
--
2
--  Front-end for SpaceWire Receiver
3
--
4
--  This entity samples the input signals DataIn and StrobeIn to detect
5
--  valid bit transitions. Received bits are handed to the application
6
--  in groups of "rxchunk" bits at a time, synchronous to the system clock.
7
--
8
--  This receiver is based on synchronous oversampling of the input signals.
9
--  Inputs are sampled on the rising and falling edges of an externally
10
--  supplied sample clock "rxclk". Therefore the maximum bitrate of the
11
--  incoming signal must be significantly lower than two times the "rxclk"
12
--  clock frequency. The maximum incoming bitrate must also be strictly
13
--  lower than rxchunk times the system clock frequency.
14
--
15
--  This code is tuned for implementation on Xilinx Spartan-3.
16
--
17
--  Details
18
--  -------
19
--
20
--  Stage A: The inputs "spw_di" and "spw_si" are handled as DDR signals,
21
--  synchronously sampled on both edges of "rxclk".
22
--
23
--  Stage B: The input signals are re-registered on the rising edge of "rxclk"
24
--  for further processing. This implies that every rising edge of "rxclk"
25
--  produces two new samples of "spw_di" and two new samples of "spw_si".
26
--  Some preparation is done for data/strobe decoding.
27
--
28
--  Stage C: Transitions in input signals are detected by comparing the XOR
29
--  of data and strobe to the XOR of the previous data and strobe samples.
30
--  If there is a difference, we know that either data or strobe has changed
31
--  and the new value of data is a valid new bit. Every rising edge of "rxclk"
32
--  thus produces either zero, one or two new data bits.
33
--
34
--  Received data bits are pushed into a cyclic buffer. A two-hot array marks
35
--  the two positions where the next received bits will go into the buffer.
36
--  In addition, a 4-step gray-encoded counter "headptr" indicates the current
37
--  position in the cyclic buffer.
38
--
39
--  The contents of the cyclic buffer and the head pointer are re-registered
40
--  on the rising edge of the system clock. A binary counter "tailptr" points
41
--  to next group of bits to read from the cyclic buffer. A comparison between
42
--  "tailptr" and "headptr" determines whether those bits have already been
43
--  received and safely stored in the buffer.
44
--
45
--  Implementation guidelines 
46
--  -------------------------
47
--
48
--  IOB flip-flops must be used to sample spw_di and spw_si.
49
--  Clock skew between the IOBs for spw_di and spw_si must be minimized.
50
--
51
--  "rxclk" must be at least as fast as the system clock;
52
--  "rxclk" does not need to be phase-related to the system clock;
53
--  it is allowed for "rxclk" to be equal to the system clock.
54
--
55
--  The following timing constraints are needed:
56
--   * PERIOD constraint on the system clock;
57
--   * PERIOD constraint on "rxclk";
58
--   * FROM-TO constraint from "rxclk" to system clock, equal to one "rxclk" period;
59
--   * FROM-TO constraint from system clock to "rxclk", equal to one "rxclk" period.
60
--
61
 
62
library ieee;
63
use ieee.std_logic_1164.all;
64
use ieee.numeric_std.all;
65
 
66
entity spwrecvfront_fast is
67
 
68
    generic (
69
        -- Number of bits to pass to the application per system clock.
70
        rxchunk:        integer range 1 to 4 );
71
 
72
    port (
73
        -- System clock.
74
        clk:        in  std_logic;
75
 
76
        -- Sample clock.
77
        rxclk:      in  std_logic;
78
 
79
        -- High to enable receiver; low to disable and reset receiver.
80
        rxen:       in  std_logic;
81
 
82
        -- High if there has been recent activity on the input lines.
83
        inact:      out std_logic;
84
 
85
        -- High if inbits contains a valid group of received bits.
86
        -- If inbvalid='1', the application must sample inbits on
87
        -- the rising edge of clk.
88
        inbvalid:   out std_logic;
89
 
90
        -- Received bits (bit 0 is the earliest received bit).
91
        inbits:     out std_logic_vector(rxchunk-1 downto 0);
92
 
93
        -- Data In signal from SpaceWire bus.
94
        spw_di:     in  std_logic;
95
 
96
        -- Strobe In signal from SpaceWire bus.
97
        spw_si:     in  std_logic );
98
 
99
    -- Turn off FSM extraction.
100
    -- Without this, XST will happily apply one-hot encoding to rrx.headptr.
101
    attribute FSM_EXTRACT: string;
102
    attribute FSM_EXTRACT of spwrecvfront_fast: entity is "NO";
103
 
104
    -- Turn off register replication.
105
    -- Without this, XST will happily replicate my synchronization flip-flops.
106
    attribute REGISTER_DUPLICATION: string;
107
    attribute REGISTER_DUPLICATION of spwrecvfront_fast: entity is "FALSE";
108
 
109
end entity spwrecvfront_fast;
110
 
111
architecture spwrecvfront_arch of spwrecvfront_fast is
112
 
113
    -- size of the cyclic buffer in bits;
114
    -- typically 4 times rxchunk, except when rxchunk = 1
115
    type chunk_array_type is array(1 to 4) of integer;
116
    constant chunk_to_buflen: chunk_array_type := ( 8, 8, 12, 16 );
117
    constant c_buflen: integer := chunk_to_buflen(rxchunk);
118
 
119
    -- convert from straight binary to reflected binary gray code
120
    function gray_encode(b: in std_logic_vector) return std_logic_vector is
121
        variable g: std_logic_vector(b'high downto b'low);
122
    begin
123
        g(b'high) := b(b'high);
124
        for i in b'high-1 downto b'low loop
125
            g(i) := b(i) xor b(i+1);
126
        end loop;
127
        return g;
128
    end function;
129
 
130
    -- convert from reflected binary gray code to straight binary
131
    function gray_decode(g: in std_logic_vector) return std_logic_vector is
132
        variable b: std_logic_vector(g'high downto g'low);
133
    begin
134
        b(g'high) := g(g'high);
135
        for i in g'high-1 downto g'low loop
136
            b(i) := g(i) xor b(i+1);
137
        end loop;
138
        return b;
139
    end function;
140
 
141
    -- stage A: input flip-flops for rising/falling rxclk
142
    signal s_a_di0:     std_logic;
143
    signal s_a_di1:     std_logic;
144
    signal s_a_si0:     std_logic;
145
    signal s_a_si1:     std_logic;
146
 
147
    -- registers in rxclk domain
148
    type rxregs_type is record
149
        -- reset synchronizer
150
        reset:      std_logic_vector(1 downto 0);
151
        -- stage B: re-register input samples and prepare for data/strobe decoding
152
        b_di0:      std_ulogic;
153
        b_di1:      std_ulogic;
154
        b_si1:      std_ulogic;
155
        b_xor0:     std_ulogic;     -- b_xor0 = b_di0 xor b_si0
156
        -- stage C: after data/strobe decoding
157
        c_bit:      std_logic_vector(1 downto 0);
158
        c_val:      std_logic_vector(1 downto 0);
159
        c_xor1:     std_ulogic;
160
        -- cyclic bit buffer
161
        bufdata:    std_logic_vector(c_buflen-1 downto 0);  -- data bits
162
        bufmark:    std_logic_vector(c_buflen-1 downto 0);  -- two-hot, marking destination of next two bits
163
        headptr:    std_logic_vector(1 downto 0);           -- gray encoded head position
164
        headlow:    std_logic_vector(1 downto 0);           -- least significant bits of head position
165
        headinc:    std_ulogic;                             -- must update headptr on next clock
166
        -- activity detection
167
        bitcnt:     std_logic_vector(2 downto 0);           -- gray counter
168
    end record;
169
 
170
    -- registers in system clock domain
171
    type regs_type is record
172
        -- cyclic bit buffer, re-registered to the system clock
173
        bufdata:    std_logic_vector(c_buflen-1 downto 0);  -- data bits
174
        headptr:    std_logic_vector(1 downto 0);           -- gray encoded head position
175
        -- tail pointer (binary)
176
        tailptr:    std_logic_vector(2 downto 0);
177
        -- activity detection
178
        bitcnt:     std_logic_vector(2 downto 0);
179
        bitcntp:    std_logic_vector(2 downto 0);
180
        bitcntpp:   std_logic_vector(2 downto 0);
181
        -- output registers
182
        inact:      std_ulogic;
183
        inbvalid:   std_ulogic;
184
        inbits:     std_logic_vector(rxchunk-1 downto 0);
185
        rxen:       std_ulogic;
186
    end record;
187
 
188
    -- registers
189
    signal r, rin:      regs_type;
190
    signal rrx, rrxin:  rxregs_type;
191
 
192
    -- force use of IOB flip-flops
193
    attribute IOB: string;
194
    attribute IOB of s_a_di0: signal is "TRUE";
195
    attribute IOB of s_a_di1: signal is "TRUE";
196
    attribute IOB of s_a_si0: signal is "TRUE";
197
    attribute IOB of s_a_si1: signal is "TRUE";
198
 
199
begin
200
 
201
    -- sample inputs on rising edge of rxclk
202
    process (rxclk) is
203
    begin
204
        if rising_edge(rxclk) then
205
            s_a_di0     <= spw_di;
206
            s_a_si0     <= spw_si;
207
        end if;
208
    end process;
209
 
210
    -- sample inputs on falling edge of rxclk
211
    process (rxclk) is
212
    begin
213
        if falling_edge(rxclk) then
214
            s_a_di1     <= spw_di;
215
            s_a_si1     <= spw_si;
216
        end if;
217
    end process;
218
 
219
    -- combinatorial process
220
    process  (r, rrx, rxen, s_a_di0, s_a_di1, s_a_si0, s_a_si1)
221
        variable v:     regs_type;
222
        variable vrx:   rxregs_type;
223
        variable v_i:   integer range 0 to 7;
224
        variable v_tail: std_logic_vector(1 downto 0);
225
    begin
226
        v       := r;
227
        vrx     := rrx;
228
        v_i     := 0;
229
        v_tail  := (others => '0');
230
 
231
        -- ---- SAMPLE CLOCK DOMAIN ----
232
 
233
        -- stage B: re-register input samples
234
        vrx.b_di0   := s_a_di0;
235
        vrx.b_di1   := s_a_di1;
236
        vrx.b_xor0  := s_a_di0 xor s_a_si0;
237
        vrx.b_si1   := s_a_si1;
238
 
239
        -- stage C: decode data/strobe and detect valid bits
240
        if (rrx.b_xor0 xor rrx.c_xor1) = '1' then
241
            -- b_di0 is a valid new bit
242
            vrx.c_bit(0) := rrx.b_di0;
243
        else
244
            -- skip b_di0 and try b_di1
245
            vrx.c_bit(0) := rrx.b_di1;
246
        end if;
247
        vrx.c_bit(1) := rrx.b_di1;
248
        vrx.c_val(0) := (rrx.b_xor0 xor rrx.c_xor1) or  (rrx.b_di1 xor rrx.b_si1 xor rrx.b_xor0);
249
        vrx.c_val(1) := (rrx.b_xor0 xor rrx.c_xor1) and (rrx.b_di1 xor rrx.b_si1 xor rrx.b_xor0);
250
        vrx.c_xor1   := rrx.b_di1 xor rrx.b_si1;
251
 
252
        -- Note:
253
        -- c_val = "00" if no new bits are received
254
        -- c_val = "01" if one new bit is received; the new bit is in c_bit(0)
255
        -- c_val = "11" if two new bits are received
256
 
257
        -- Note:
258
        -- bufmark contains two '1' bits in neighbouring positions, marking
259
        -- the positions that newly received bits will be written to.
260
 
261
        -- Update the cyclic buffer.
262
        for i in 0 to c_buflen-1 loop
263
            -- update data bit at position (i)
264
            if rrx.bufmark(i) = '1' then
265
                if rrx.bufmark((i+1) mod rrx.bufmark'length) = '1' then
266
                    -- this is the first of the two marked positions;
267
                    -- put the first received bit here (if any)
268
                    vrx.bufdata(i) := rrx.c_bit(0);
269
                else
270
                    -- this is the second of the two marked positions;
271
                    -- put the second received bit here (if any)
272
                    vrx.bufdata(i) := rrx.c_bit(1);
273
                end if;
274
            end if;
275
            -- update marker at position (i)
276
            if rrx.c_val(0) = '1' then
277
                if rrx.c_val(1) = '1' then
278
                    -- shift two positions
279
                    vrx.bufmark(i) := rrx.bufmark((i+rrx.bufmark'length-2) mod rrx.bufmark'length);
280
                else
281
                    -- shift one position
282
                    vrx.bufmark(i) := rrx.bufmark((i+rrx.bufmark'length-1) mod rrx.bufmark'length);
283
                end if;
284
            end if;
285
        end loop;
286
 
287
        -- Update "headlow", the least significant bits of the head position.
288
        -- This is a binary counter from 0 to rxchunk-1, or from 0 to 1
289
        -- if rxchunk = 1. If the counter overflows, "headptr" will be
290
        -- updated in the next clock cycle.
291
        case rxchunk is
292
            when 1 | 2 =>
293
                -- count from "00" to "01"
294
                if rrx.c_val(1) = '1' then      -- got two new bits
295
                    vrx.headlow(0) := rrx.headlow(0);
296
                    vrx.headinc    := '1';
297
                elsif rrx.c_val(0) = '1' then   -- got one new bit
298
                    vrx.headlow(0) := not rrx.headlow(0);
299
                    vrx.headinc    := rrx.headlow(0);
300
                else                            -- got nothing
301
                    vrx.headlow(0) := rrx.headlow(0);
302
                    vrx.headinc    := '0';
303
                end if;
304
            when 3 =>
305
                -- count from "00" to "10"
306
                if rrx.c_val(1) = '1' then      -- got two new bits
307
                    case rrx.headlow is
308
                        when "00" =>   vrx.headlow := "10";
309
                        when "01" =>   vrx.headlow := "00";
310
                        when others => vrx.headlow := "01";
311
                    end case;
312
                    vrx.headinc := rrx.headlow(0) or rrx.headlow(1);
313
                elsif rrx.c_val(0) = '1' then   -- got one new bit
314
                    if rrx.headlow(1) = '1' then
315
                        vrx.headlow := "00";
316
                        vrx.headinc := '1';
317
                    else
318
                        vrx.headlow(0) := not rrx.headlow(0);
319
                        vrx.headlow(1) := rrx.headlow(0);
320
                        vrx.headinc    := '0';
321
                    end if;
322
                else                            -- got nothing
323
                    vrx.headlow := rrx.headlow;
324
                    vrx.headinc := '0';
325
                end if;
326
            when 4 =>
327
                -- count from "00" to "11"
328
                if rrx.c_val(1) = '1' then      -- got two new bits
329
                    vrx.headlow(0) := rrx.headlow(0);
330
                    vrx.headlow(1) := not rrx.headlow(1);
331
                    vrx.headinc    := rrx.headlow(1);
332
                elsif rrx.c_val(0) = '1' then   -- got one new bit
333
                    vrx.headlow(0) := not rrx.headlow(0);
334
                    vrx.headlow(1) := rrx.headlow(1) xor rrx.headlow(0);
335
                    vrx.headinc    := rrx.headlow(0) and rrx.headlow(1);
336
                else                            -- got nothing
337
                    vrx.headlow := rrx.headlow;
338
                    vrx.headinc := '0';
339
                end if;
340
        end case;
341
 
342
        -- Update the gray-encoded head position.
343
        if rrx.headinc = '1' then
344
            case rrx.headptr is
345
                when "00" =>   vrx.headptr := "01";
346
                when "01" =>   vrx.headptr := "11";
347
                when "11" =>   vrx.headptr := "10";
348
                when others => vrx.headptr := "00";
349
            end case;
350
        end if;
351
 
352
        -- Activity detection.
353
        if rrx.c_val(0) = '1' then
354
            vrx.bitcnt  := gray_encode(
355
                std_logic_vector(unsigned(gray_decode(rrx.bitcnt)) + 1));
356
        end if;
357
 
358
        -- Synchronize reset signal for rxclk domain.
359
        if r.rxen = '0' then
360
            vrx.reset   := "11";
361
        else
362
            vrx.reset   := "0" & rrx.reset(1);
363
        end if;
364
 
365
        -- Synchronous reset of rxclk domain.
366
        if rrx.reset(0) = '1' then
367
            vrx.bufmark := (0 => '1', 1 => '1', others => '0');
368
            vrx.headptr := "00";
369
            vrx.headlow := "00";
370
            vrx.headinc := '0';
371
            vrx.bitcnt  := "000";
372
        end if;
373
 
374
        -- ---- SYSTEM CLOCK DOMAIN ----
375
 
376
        -- Re-register cyclic buffer and head pointer in the system clock domain.
377
        v.bufdata   := rrx.bufdata;
378
        v.headptr   := rrx.headptr;
379
 
380
        -- Increment tailptr if there was new data on the previous clock.
381
        if r.inbvalid = '1' then
382
            v.tailptr   := std_logic_vector(unsigned(r.tailptr) + 1);
383
        end if;
384
 
385
        -- Compare tailptr to headptr to decide whether there is new data.
386
        -- If the values are equal, we are about to read data which were not
387
        -- yet released by the rxclk domain
388
        -- Note: headptr is gray-coded while tailptr is normal binary.
389
        if rxchunk = 1 then
390
            -- headptr counts blocks of 2 bits while tailptr counts single bits
391
            v_tail      := v.tailptr(2 downto 1);
392
        else
393
            -- headptr and tailptr both count blocks of rxchunk bits
394
            v_tail      := v.tailptr(1 downto 0);
395
        end if;
396
        if (r.headptr(1) = v_tail(1)) and
397
           ((r.headptr(0) xor r.headptr(1)) = v_tail(0)) then
398
            -- pointers have the same value
399
            v.inbvalid  := '0';
400
        else
401
            v.inbvalid  := '1';
402
        end if;
403
 
404
        -- Multiplex bits from the cyclic buffer into the output register.
405
        if rxen = '1' then
406
            if rxchunk = 1 then
407
                -- cyclic buffer contains 8 slots of 1 bit wide
408
                v_i         := to_integer(unsigned(v.tailptr));
409
                v.inbits    := r.bufdata(v_i downto v_i);
410
            else
411
                -- cyclic buffer contains 4 slots of rxchunk bits wide
412
                v_i         := to_integer(unsigned(v.tailptr(1 downto 0)));
413
                v.inbits    := r.bufdata(rxchunk*v_i+rxchunk-1 downto rxchunk*v_i);
414
            end if;
415
        end if;
416
 
417
        -- Activity detection.
418
        v.bitcnt    := rrx.bitcnt;
419
        v.bitcntp   := r.bitcnt;
420
        v.bitcntpp  := r.bitcntp;
421
        if rxen = '1' then
422
            if r.bitcntp = r.bitcntpp then
423
                v.inact     := r.inbvalid;
424
            else
425
                v.inact     := '1';
426
            end if;
427
        end if;
428
 
429
        -- Synchronous reset of system clock domain.
430
        if rxen = '0' then
431
            v.tailptr   := "000";
432
            v.inact     := '0';
433
            v.inbvalid  := '0';
434
            v.inbits    := (others => '0');
435
        end if;
436
 
437
        -- Register rxen to ensure glitch-free signal to rxclk domain
438
        v.rxen      := rxen;
439
 
440
        -- drive outputs
441
        inact       <= r.inact;
442
        inbvalid    <= r.inbvalid;
443
        inbits      <= r.inbits;
444
 
445
        -- update registers
446
        rrxin       <= vrx;
447
        rin         <= v;
448
 
449
    end process;
450
 
451
    -- update registers on rising edge of rxclk
452
    process (rxclk) is
453
    begin
454
        if rising_edge(rxclk) then
455
            rrx <= rrxin;
456
        end if;
457
    end process;
458
 
459
    -- update registers on rising edge of system clock
460
    process (clk) is
461
    begin
462
        if rising_edge(clk) then
463
            r <= rin;
464
        end if;
465
    end process;
466
 
467
end architecture spwrecvfront_arch;

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