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[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwrecvfront_fast.vhd] - Blame information for rev 7

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1 2 jorisvr
--
2
--  Front-end for SpaceWire Receiver
3
--
4
--  This entity samples the input signals DataIn and StrobeIn to detect
5
--  valid bit transitions. Received bits are handed to the application
6
--  in groups of "rxchunk" bits at a time, synchronous to the system clock.
7
--
8
--  This receiver is based on synchronous oversampling of the input signals.
9
--  Inputs are sampled on the rising and falling edges of an externally
10
--  supplied sample clock "rxclk". Therefore the maximum bitrate of the
11
--  incoming signal must be significantly lower than two times the "rxclk"
12
--  clock frequency. The maximum incoming bitrate must also be strictly
13
--  lower than rxchunk times the system clock frequency.
14
--
15
--  This code is tuned for implementation on Xilinx Spartan-3.
16
--
17
--  Details
18
--  -------
19
--
20
--  Stage A: The inputs "spw_di" and "spw_si" are handled as DDR signals,
21
--  synchronously sampled on both edges of "rxclk".
22
--
23
--  Stage B: The input signals are re-registered on the rising edge of "rxclk"
24
--  for further processing. This implies that every rising edge of "rxclk"
25
--  produces two new samples of "spw_di" and two new samples of "spw_si".
26
--
27
--  Stage C: Transitions in input signals are detected by comparing the XOR
28
--  of data and strobe to the XOR of the previous data and strobe samples.
29
--  If there is a difference, we know that either data or strobe has changed
30
--  and the new value of data is a valid new bit. Every rising edge of "rxclk"
31 7 jorisvr
--  thus produces either zero, or one or two new data bits.
32 2 jorisvr
--
33 7 jorisvr
--  Stage D: Received bits are collected in groups of "rxchunk" bits
34
--  (unless rxchunk=1, in which case groups of 2 bits are used). Complete
35
--  groups are pushed into an 8-deep cyclic buffer. A 3-bit counter "headptr"
36
--  indicates the current position in the cyclic buffer.
37 2 jorisvr
--
38 7 jorisvr
--  The system clock domain reads bit groups from the cyclic buffer. A tail
39
--  pointer indicates the next location to read from the buffer. A comparison
40
--  between the "tailptr" and a re-synchronized copy of the "headptr" determines
41
--  whether valid bits are available in the buffer.
42 2 jorisvr
--
43 7 jorisvr
--  Activity detection is based on a 3-bit counter "bitcnt". This counter is
44
--  incremented whenever the rxclk domain receives 1 or 2 new bits. The system
45
--  clock domain monitors a re-synchronized copy of the activity counter to
46
--  determine whether it has been updated since the previous system clock cycle.
47
--
48 2 jorisvr
--  Implementation guidelines 
49
--  -------------------------
50
--
51
--  IOB flip-flops must be used to sample spw_di and spw_si.
52
--  Clock skew between the IOBs for spw_di and spw_si must be minimized.
53
--
54
--  "rxclk" must be at least as fast as the system clock;
55
--  "rxclk" does not need to be phase-related to the system clock;
56
--  it is allowed for "rxclk" to be equal to the system clock.
57
--
58
--  The following timing constraints are needed:
59
--   * PERIOD constraint on the system clock;
60
--   * PERIOD constraint on "rxclk";
61
--   * FROM-TO constraint from "rxclk" to system clock, equal to one "rxclk" period;
62
--   * FROM-TO constraint from system clock to "rxclk", equal to one "rxclk" period.
63
--
64
 
65
library ieee;
66
use ieee.std_logic_1164.all;
67
use ieee.numeric_std.all;
68 7 jorisvr
use work.spwpkg.all;
69 2 jorisvr
 
70
entity spwrecvfront_fast is
71
 
72
    generic (
73
        -- Number of bits to pass to the application per system clock.
74
        rxchunk:        integer range 1 to 4 );
75
 
76
    port (
77
        -- System clock.
78
        clk:        in  std_logic;
79
 
80
        -- Sample clock.
81
        rxclk:      in  std_logic;
82
 
83
        -- High to enable receiver; low to disable and reset receiver.
84
        rxen:       in  std_logic;
85
 
86
        -- High if there has been recent activity on the input lines.
87
        inact:      out std_logic;
88
 
89
        -- High if inbits contains a valid group of received bits.
90
        -- If inbvalid='1', the application must sample inbits on
91
        -- the rising edge of clk.
92
        inbvalid:   out std_logic;
93
 
94
        -- Received bits (bit 0 is the earliest received bit).
95
        inbits:     out std_logic_vector(rxchunk-1 downto 0);
96
 
97
        -- Data In signal from SpaceWire bus.
98
        spw_di:     in  std_logic;
99
 
100
        -- Strobe In signal from SpaceWire bus.
101
        spw_si:     in  std_logic );
102
 
103
    -- Turn off FSM extraction.
104
    -- Without this, XST will happily apply one-hot encoding to rrx.headptr.
105
    attribute FSM_EXTRACT: string;
106
    attribute FSM_EXTRACT of spwrecvfront_fast: entity is "NO";
107
 
108
end entity spwrecvfront_fast;
109
 
110
architecture spwrecvfront_arch of spwrecvfront_fast is
111
 
112 7 jorisvr
    -- width of bit groups in cyclic buffer;
113
    -- typically equal to rxchunk, except when rxchunk = 1
114
    type memwidth_array_type is array(1 to 4) of integer;
115
    constant chunk_to_memwidth: memwidth_array_type := ( 2, 2, 3, 4 );
116
    constant memwidth: integer := chunk_to_memwidth(rxchunk);
117 2 jorisvr
 
118
    -- registers in rxclk domain
119
    type rxregs_type is record
120 7 jorisvr
        -- stage B: re-register input samples
121 2 jorisvr
        b_di0:      std_ulogic;
122 7 jorisvr
        b_si0:      std_ulogic;
123 2 jorisvr
        b_di1:      std_ulogic;
124
        b_si1:      std_ulogic;
125 7 jorisvr
        -- stage C: data/strobe decoding
126 2 jorisvr
        c_bit:      std_logic_vector(1 downto 0);
127
        c_val:      std_logic_vector(1 downto 0);
128
        c_xor1:     std_ulogic;
129 7 jorisvr
        -- stage D: collect groups of memwidth bits
130
        d_shift:    std_logic_vector(memwidth-1 downto 0);
131
        d_count:    std_logic_vector(memwidth-1 downto 0);
132
        -- cyclic buffer access
133
        bufdata:    std_logic_vector(memwidth-1 downto 0);
134
        bufwrite:   std_ulogic;
135
        headptr:    std_logic_vector(2 downto 0);
136 2 jorisvr
        -- activity detection
137 7 jorisvr
        bitcnt:     std_logic_vector(2 downto 0);
138 2 jorisvr
    end record;
139
 
140
    -- registers in system clock domain
141
    type regs_type is record
142 7 jorisvr
        -- data path from buffer to output
143 2 jorisvr
        tailptr:    std_logic_vector(2 downto 0);
144 7 jorisvr
        inbvalid:   std_ulogic;
145
        -- split 2-bit groups if rxchunk=1
146
        splitbit:   std_ulogic;
147
        splitinx:   std_ulogic;
148
        splitvalid: std_ulogic;
149 2 jorisvr
        -- activity detection
150
        bitcntp:    std_logic_vector(2 downto 0);
151
        inact:      std_ulogic;
152 7 jorisvr
        -- reset signal towards rxclk domain
153
        rxdis:      std_ulogic;
154 2 jorisvr
    end record;
155
 
156 7 jorisvr
    constant regs_reset: regs_type := (
157
        tailptr     => "000",
158
        inbvalid    => '0',
159
        splitbit    => '0',
160
        splitinx    => '0',
161
        splitvalid  => '0',
162
        bitcntp     => "000",
163
        inact       => '0',
164
        rxdis       => '1' );
165
 
166
    -- Signals that are re-synchronized from rxclk to system clock domain.
167
    type syncsys_type is record
168
        headptr:    std_logic_vector(2 downto 0);   -- pointer in cyclic buffer
169
        bitcnt:     std_logic_vector(2 downto 0);   -- activity detection
170
    end record;
171
 
172
    -- Registers.
173
    signal r:           regs_type := regs_reset;
174
    signal rin:         regs_type;
175 2 jorisvr
    signal rrx, rrxin:  rxregs_type;
176
 
177 7 jorisvr
    -- Synchronized signals after crossing clock domains.
178
    signal syncrx_rstn: std_logic;
179
    signal syncsys:     syncsys_type;
180
 
181
    -- Output data from cyclic buffer.
182
    signal s_bufdout:   std_logic_vector(memwidth-1 downto 0);
183
 
184
    -- stage A: input flip-flops for rising/falling rxclk
185
    signal s_a_di0:     std_logic;
186
    signal s_a_si0:     std_logic;
187
    signal s_a_di1:     std_logic;
188
    signal s_a_si1:     std_logic;
189
    signal s_a_di2:     std_logic;
190
    signal s_a_si2:     std_logic;
191
 
192 2 jorisvr
    -- force use of IOB flip-flops
193
    attribute IOB: string;
194
    attribute IOB of s_a_di1: signal is "TRUE";
195
    attribute IOB of s_a_si1: signal is "TRUE";
196 7 jorisvr
    attribute IOB of s_a_di2: signal is "TRUE";
197
    attribute IOB of s_a_si2: signal is "TRUE";
198 2 jorisvr
 
199
begin
200
 
201 7 jorisvr
    -- Cyclic data buffer.
202
    bufmem: spwram
203
        generic map (
204
            abits   => 3,
205
            dbits   => memwidth )
206
        port map (
207
            rclk    => clk,
208
            wclk    => rxclk,
209
            ren     => '1',
210
            raddr   => r.tailptr,
211
            rdata   => s_bufdout,
212
            wen     => rrx.bufwrite,
213
            waddr   => rrx.headptr,
214
            wdata   => rrx.bufdata );
215
 
216
    -- Synchronize reset signal for rxclk domain.
217
    syncrx_reset: syncdff
218
        port map ( clk => rxclk, rst => r.rxdis, di => '1', do => syncrx_rstn );
219
 
220
    -- Synchronize signals from rxclk domain to system clock domain.
221
    syncsys_headptr0: syncdff
222
        port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(0), do => syncsys.headptr(0) );
223
    syncsys_headptr1: syncdff
224
        port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(1), do => syncsys.headptr(1) );
225
    syncsys_headptr2: syncdff
226
        port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(2), do => syncsys.headptr(2) );
227
    syncsys_bitcnt0: syncdff
228
        port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(0), do => syncsys.bitcnt(0) );
229
    syncsys_bitcnt1: syncdff
230
        port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(1), do => syncsys.bitcnt(1) );
231
    syncsys_bitcnt2: syncdff
232
        port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(2), do => syncsys.bitcnt(2) );
233
 
234 2 jorisvr
    -- sample inputs on rising edge of rxclk
235
    process (rxclk) is
236
    begin
237
        if rising_edge(rxclk) then
238 7 jorisvr
            s_a_di1     <= spw_di;
239
            s_a_si1     <= spw_si;
240 2 jorisvr
        end if;
241
    end process;
242
 
243
    -- sample inputs on falling edge of rxclk
244
    process (rxclk) is
245
    begin
246
        if falling_edge(rxclk) then
247 7 jorisvr
            s_a_di2     <= spw_di;
248
            s_a_si2     <= spw_si;
249
            -- reregister inputs in fabric flip-flops
250
            s_a_di0     <= s_a_di2;
251
            s_a_si0     <= s_a_si2;
252 2 jorisvr
        end if;
253
    end process;
254
 
255
    -- combinatorial process
256 7 jorisvr
    process  (r, rrx, rxen, syncrx_rstn, syncsys, s_bufdout, s_a_di0, s_a_si0, s_a_di1, s_a_si1)
257 2 jorisvr
        variable v:     regs_type;
258
        variable vrx:   rxregs_type;
259
    begin
260
        v       := r;
261
        vrx     := rrx;
262
 
263
        -- ---- SAMPLE CLOCK DOMAIN ----
264
 
265
        -- stage B: re-register input samples
266
        vrx.b_di0   := s_a_di0;
267 7 jorisvr
        vrx.b_si0   := s_a_si0;
268 2 jorisvr
        vrx.b_di1   := s_a_di1;
269
        vrx.b_si1   := s_a_si1;
270
 
271
        -- stage C: decode data/strobe and detect valid bits
272 7 jorisvr
        if (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) = '1' then
273 2 jorisvr
            vrx.c_bit(0) := rrx.b_di0;
274
        else
275
            vrx.c_bit(0) := rrx.b_di1;
276
        end if;
277
        vrx.c_bit(1) := rrx.b_di1;
278 7 jorisvr
        vrx.c_val(0) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) or
279
                        (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1);
280
        vrx.c_val(1) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) and
281
                        (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1);
282 2 jorisvr
        vrx.c_xor1   := rrx.b_di1 xor rrx.b_si1;
283
 
284
        -- Note:
285
        -- c_val = "00" if no new bits are received
286
        -- c_val = "01" if one new bit is received; the new bit is in c_bit(0)
287
        -- c_val = "11" if two new bits are received
288
 
289 7 jorisvr
        -- stage D: collect groups of memwidth bits
290
        if rrx.c_val(0) = '1' then
291 2 jorisvr
 
292 7 jorisvr
            -- shift incoming bits into register
293
            if rrx.c_val(1) = '1' then
294
                vrx.d_shift := rrx.c_bit & rrx.d_shift(memwidth-1 downto 2);
295
            else
296
                vrx.d_shift := rrx.c_bit(0) & rrx.d_shift(memwidth-1 downto 1);
297 2 jorisvr
            end if;
298 7 jorisvr
 
299
            -- prepare to store a group of memwidth bits
300
            if rrx.d_count(0) = '1' then
301
                -- only one more bit needed
302
                vrx.bufdata := rrx.c_bit(0) & rrx.d_shift(memwidth-1 downto 1);
303
            else
304
                vrx.bufdata := rrx.c_bit & rrx.d_shift(memwidth-1 downto 2);
305 2 jorisvr
            end if;
306
 
307 7 jorisvr
            -- countdown nr of needed bits (one-hot counter)
308
            if rrx.c_val(1) = '1' then
309
                vrx.d_count := rrx.d_count(1 downto 0) & rrx.d_count(memwidth-1 downto 2);
310
            else
311
                vrx.d_count := rrx.d_count(0 downto 0) & rrx.d_count(memwidth-1 downto 1);
312
            end if;
313 2 jorisvr
 
314
        end if;
315
 
316 7 jorisvr
        -- stage D: store groups of memwidth bits
317
        vrx.bufwrite := rrx.c_val(0) and (rrx.d_count(0) or (rrx.c_val(1) and rrx.d_count(1)));
318
 
319
        -- Increment head pointer.
320
        if rrx.bufwrite = '1' then
321
            vrx.headptr := std_logic_vector(unsigned(rrx.headptr) + 1);
322
        end if;
323
 
324 2 jorisvr
        -- Activity detection.
325
        if rrx.c_val(0) = '1' then
326 7 jorisvr
            vrx.bitcnt  := std_logic_vector(unsigned(rrx.bitcnt) + 1);
327 2 jorisvr
        end if;
328
 
329
        -- Synchronous reset of rxclk domain.
330 7 jorisvr
        if syncrx_rstn = '0' then
331
            vrx.c_val   := "00";
332
            vrx.c_xor1  := '0';
333
            vrx.d_count := (others => '0');
334
            vrx.d_count(memwidth-1) := '1';
335
            vrx.bufwrite := '0';
336
            vrx.headptr := "000";
337 2 jorisvr
            vrx.bitcnt  := "000";
338
        end if;
339
 
340
        -- ---- SYSTEM CLOCK DOMAIN ----
341
 
342
        -- Compare tailptr to headptr to decide whether there is new data.
343 7 jorisvr
        -- If the values are equal, we are about to read a location which has
344
        -- not yet been written by the rxclk domain.
345
        if r.tailptr = syncsys.headptr then
346
            -- No more data in cyclic buffer.
347 2 jorisvr
            v.inbvalid  := '0';
348
        else
349 7 jorisvr
            -- Reading valid data from cyclic buffer.
350 2 jorisvr
            v.inbvalid  := '1';
351 7 jorisvr
            -- Increment tail pointer.
352
            if rxchunk /= 1 then
353
                v.tailptr   := std_logic_vector(unsigned(r.tailptr) + 1);
354
            end if;
355 2 jorisvr
        end if;
356 7 jorisvr
 
357
        -- If rxchunk=1, split 2-bit groups into separate bits.
358
        if rxchunk = 1 then
359
            -- Select one of the two bits.
360
            if r.splitinx = '0' then
361
                v.splitbit  := s_bufdout(0);
362 2 jorisvr
            else
363 7 jorisvr
                v.splitbit  := s_bufdout(1);
364 2 jorisvr
            end if;
365 7 jorisvr
            -- Indicate valid bit.
366
            v.splitvalid := r.inbvalid;
367
            -- Increment tail pointer.
368
            if r.inbvalid = '1' then
369
                v.splitinx   := not r.splitinx;
370
                if r.splitinx = '0' then
371
                    v.tailptr   := std_logic_vector(unsigned(r.tailptr) + 1);
372
                end if;
373
            end if;
374 2 jorisvr
        end if;
375
 
376
        -- Activity detection.
377 7 jorisvr
        v.bitcntp   := syncsys.bitcnt;
378
        if r.bitcntp = syncsys.bitcnt then
379
            v.inact     := '0';
380
        else
381
            v.inact     := '1';
382 2 jorisvr
        end if;
383
 
384
        -- Synchronous reset of system clock domain.
385
        if rxen = '0' then
386 7 jorisvr
            v   := regs_reset;
387 2 jorisvr
        end if;
388
 
389
        -- Register rxen to ensure glitch-free signal to rxclk domain
390 7 jorisvr
        v.rxdis     := not rxen;
391 2 jorisvr
 
392
        -- drive outputs
393
        inact       <= r.inact;
394 7 jorisvr
        if rxchunk = 1 then
395
            inbvalid    <= r.splitvalid;
396
            inbits(0)   <= r.splitbit;
397
        else
398
            inbvalid    <= r.inbvalid;
399
            inbits      <= s_bufdout;
400
        end if;
401 2 jorisvr
 
402
        -- update registers
403
        rrxin       <= vrx;
404
        rin         <= v;
405
 
406
    end process;
407
 
408
    -- update registers on rising edge of rxclk
409
    process (rxclk) is
410
    begin
411
        if rising_edge(rxclk) then
412
            rrx <= rrxin;
413
        end if;
414
    end process;
415
 
416
    -- update registers on rising edge of system clock
417
    process (clk) is
418
    begin
419
        if rising_edge(clk) then
420
            r <= rin;
421
        end if;
422
    end process;
423
 
424
end architecture spwrecvfront_arch;

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