OpenCores
URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwrecvfront_generic.vhd] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jorisvr
--
2
--  Front-end for SpaceWire Receiver
3
--
4
--  This entity samples the input signals DataIn and StrobeIn to detect
5
--  valid bit transitions. Received bits are handed to the application.
6
--
7
--  Inputs are sampled on the rising edge of the system clock, therefore
8
--  the maximum bitrate of the incoming signal must be significantly lower
9
--  than system clock frequency.
10
--
11
 
12
library ieee;
13
use ieee.std_logic_1164.all;
14
use ieee.numeric_std.all;
15
 
16
entity spwrecvfront_generic is
17
 
18
    port (
19
        -- System clock.
20
        clk:        in  std_logic;
21
 
22
        -- High to enable receiver; low to disable and reset receiver.
23
        rxen:       in  std_logic;
24
 
25
        -- High if there has been recent activity on the input lines.
26
        inact:      out std_logic;
27
 
28
        -- High if inbits contains a valid received bit.
29
        -- If inbvalid='1', the application must sample inbits on
30
        -- the rising edge of clk.
31
        inbvalid:   out std_logic;
32
 
33
        -- Received bit
34
        inbits:     out std_logic_vector(0 downto 0);
35
 
36
        -- Data In signal from SpaceWire bus.
37
        spw_di:     in  std_logic;
38
 
39
        -- Strobe In signal from SpaceWire bus.
40
        spw_si:     in  std_logic );
41
 
42
end entity spwrecvfront_generic;
43
 
44
architecture spwrecvfront_arch of spwrecvfront_generic is
45
 
46
    -- input flip-flops
47
    signal s_spwdi1:    std_ulogic;
48
    signal s_spwsi1:    std_ulogic;
49
    signal s_spwdi2:    std_ulogic;
50
    signal s_spwsi2:    std_ulogic;
51
 
52
    -- data/strobe decoding
53
    signal s_spwsi3:    std_ulogic;
54
 
55
    -- output registers
56
    signal s_inbvalid:  std_ulogic;
57
    signal s_inbit:     std_ulogic;
58
 
59
begin
60
 
61
    -- drive outputs
62
    inact       <= s_inbvalid;
63
    inbvalid    <= s_inbvalid;
64
    inbits(0)   <= s_inbit;
65
 
66
    -- synchronous process
67
    process (clk) is
68
    begin
69
        if rising_edge(clk) then
70
 
71
            -- sample input signal
72
            s_spwdi1    <= spw_di;
73
            s_spwsi1    <= spw_si;
74
 
75
            -- more flip-flops for safe synchronization
76
            s_spwdi2    <= s_spwdi1;
77
            s_spwsi2    <= s_spwsi1;
78
 
79
            -- keep strobe signal for data/strobe decoding
80
            s_spwsi3    <= s_spwsi2;
81
 
82
            if rxen = '1' then
83
                -- data/strobe decoding
84
                s_inbit     <= s_spwdi2;
85
                s_inbvalid  <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3;
86
            else
87
                -- reset receiver
88
                s_inbit     <= '0';
89
                s_inbvalid  <= '0';
90
            end if;
91
 
92
        end if;
93
    end process;
94
 
95
end architecture spwrecvfront_arch;

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.