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1 2 jorisvr
--
2
--  SpaceWire core with character-stream interface.
3
--
4
--  This entity provides a SpaceWire core with a character-stream interface.
5
--  The interface provides means for connection initiation, sending and
6
--  receiving of N-Chars and TimeCodes, and error reporting.
7
--
8
--  This entity instantiates spwlink, spwrecv, spwxmit and one of the
9
--  spwrecvfront implementations. It also implements a receive FIFO and
10
--  a transmit FIFO.
11
--
12
--  The SpaceWire standard requires that each transceiver use an initial
13
--  signalling rate of 10 Mbit/s. This implies that the system clock frequency
14
--  must be a multiple of 10 MHz. See the datasheet for further details on
15
--  bitrates and clocking.
16
--
17
 
18
library ieee;
19
use ieee.std_logic_1164.all;
20
use ieee.numeric_std.all;
21
use work.spwpkg.all;
22
 
23
entity spwstream is
24
 
25
    generic (
26
        -- System clock frequency in Hz.
27
        -- This must be set to the frequency of "clk". It is used to setup
28
        -- counters for reset timing, disconnect timeout and to transmit
29
        -- at 10 Mbit/s during the handshake.
30
        sysfreq:        real;
31
 
32
        -- Selection of a receiver front-end implementation.
33
        rximpl:         spw_implementation_type := impl_generic;
34
 
35
        -- Maximum number of bits received per system clock
36
        -- (must be 1 in case of impl_generic).
37
        rxchunk:        integer range 1 to 4 := 1;
38
 
39
        -- Selection of a transmitter implementation.
40
        tximpl:         spw_implementation_type := impl_generic;
41
 
42
        -- Size of the receive FIFO as the 2-logarithm of the number of bytes.
43
        -- Must be at least 6 (64 bytes).
44
        rxfifosize_bits: integer range 6 to 14 := 11;
45
 
46
        -- Size of the transmit FIFO as the 2-logarithm of the number of bytes.
47
        txfifosize_bits: integer range 2 to 14 := 11
48
    );
49
 
50
    port (
51
        -- System clock.
52
        clk:        in  std_logic;
53
 
54
        -- Receiver sample clock (only for impl_fast)
55
        rxclk:      in  std_logic;
56
 
57
        -- Transmit clock (only for impl_fast)
58
        txclk:      in  std_logic;
59
 
60
        -- Synchronous reset (active-high).
61
        rst:        in  std_logic;
62
 
63
        -- Enables automatic link start on receipt of a NULL character.
64
        autostart:  in  std_logic;
65
 
66
        -- Enables link start once the Ready state is reached.
67
        -- Without autostart or linkstart, the link remains in state Ready.
68
        linkstart:  in  std_logic;
69
 
70
        -- Do not start link (overrides linkstart and autostart) and/or disconnect
71
        -- if the link is in state Run.
72
        linkdis:    in  std_logic;
73
 
74
        -- Scaling factor minus 1, used to scale the system clock into the transmission
75
        -- signalling rate. The system clock is divided by (unsigned(divcnt) + 1).
76
        -- Changing this signal will immediately change the transmission rate.
77
        -- During link setup, the transmission rate is always 10 Mbit/s.
78
        txdivcnt:   in  std_logic_vector(7 downto 0);
79
 
80
        -- High for one clock cycle to request transmission of a TimeCode.
81
        -- The request is registered inside the entity until it can be processed.
82
        tick_in:    in  std_logic;
83
 
84
        -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
85
        ctrl_in:    in  std_logic_vector(1 downto 0);
86
 
87
        -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
88
        time_in:    in  std_logic_vector(5 downto 0);
89
 
90
        -- Pulled high by the application to write an N-Char to the transmit
91
        -- queue. If "txwrite" and "txrdy" are both high on the rising edge
92
        -- of "clk", a character is added to the transmit queue.
93
        -- This signal has no effect if "txrdy" is low.
94
        txwrite:    in  std_logic;
95
 
96
        -- Control flag to be sent with the next N_Char.
97
        -- Must be valid while txwrite is high.
98
        txflag:     in  std_logic;
99
 
100
        -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
101
        -- Must be valid while txwrite is high.
102
        txdata:     in  std_logic_vector(7 downto 0);
103
 
104
        -- High if the entity is ready to accept an N-Char for transmission.
105
        txrdy:      out std_logic;
106
 
107
        -- High if the transmission queue is at least half full.
108
        txhalff:    out std_logic;
109
 
110
        -- High for one clock cycle if a TimeCode was just received.
111
        tick_out:   out std_logic;
112
 
113
        -- Control bits of the last received TimeCode.
114
        ctrl_out:   out std_logic_vector(1 downto 0);
115
 
116
        -- Counter value of the last received TimeCode.
117
        time_out:   out std_logic_vector(5 downto 0);
118
 
119
        -- High if "rxflag" and "rxdata" contain valid data.
120
        -- This signal is high unless the receive FIFO is empty.
121
        rxvalid:    out std_logic;
122
 
123
        -- High if the receive FIFO is at least half full.
124
        rxhalff:    out std_logic;
125
 
126
        -- High if the received character is EOP or EEP; low if the received
127
        -- character is a data byte. Valid if "rxvalid" is high.
128
        rxflag:     out std_logic;
129
 
130
        -- Received byte, or "00000000" for EOP or "00000001" for EEP.
131
        -- Valid if "rxvalid" is high.
132
        rxdata:     out std_logic_vector(7 downto 0);
133
 
134
        -- Pulled high by the application to accept a received character.
135
        -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
136
        -- a character is removed from the receive FIFO and "rxvalid", "rxflag"
137
        -- and "rxdata" are updated.
138
        -- This signal has no effect if "rxvalid" is low.
139
        rxread:     in  std_logic;
140
 
141
        -- High if the link state machine is currently in the Started state.
142
        started:    out std_logic;
143
 
144
        -- High if the link state machine is currently in the Connecting state.
145
        connecting: out std_logic;
146
 
147
        -- High if the link state machine is currently in the Run state, indicating
148
        -- that the link is fully operational. If none of started, connecting or running
149
        -- is high, the link is in an initial state and the transmitter is not yet enabled.
150
        running:    out std_logic;
151
 
152
        -- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
153
        -- This indication is auto-clearing.
154
        errdisc:    out std_logic;
155
 
156
        -- Parity error detected in state Run. Triggers a reset and reconnect of the link.
157
        -- This indication is auto-clearing.
158
        errpar:     out std_logic;
159
 
160
        -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
161
        -- the link. This indication is auto-clearing.
162
        erresc:     out std_logic;
163
 
164
        -- Credit error detected. Triggers a reset and reconnect of the link.
165
        -- This indication is auto-clearing.
166
        errcred:    out std_logic;
167
 
168
        -- Data In signal from SpaceWire bus.
169
        spw_di:     in  std_logic;
170
 
171
        -- Strobe In signal from SpaceWire bus.
172
        spw_si:     in  std_logic;
173
 
174
        -- Data Out signal to SpaceWire bus.
175
        spw_do:     out std_logic;
176
 
177
        -- Strobe Out signal to SpaceWire bus.
178
        spw_so:     out std_logic
179
    );
180
 
181
end entity spwstream;
182
 
183
architecture spwstream_arch of spwstream is
184
 
185
    -- Convert boolean to std_logic.
186
    type bool_to_logic_type is array(boolean) of std_ulogic;
187
    constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
188
 
189
    -- Reset time (6.4 us) in system clocks
190
    constant reset_time:        integer := integer(sysfreq * 6.4e-6);
191
 
192
    -- Disconnect time (850 ns) in system clocks
193
    constant disconnect_time:   integer := integer(sysfreq * 850.0e-9);
194
 
195
    -- Initial tx clock scaler (10 Mbit).
196
    constant default_divcnt:    std_logic_vector(7 downto 0) :=
197
        std_logic_vector(to_unsigned(integer(sysfreq / 10.0e6 - 1.0), 8));
198
 
199
    -- Registers.
200
    type regs_type is record
201
        -- packet state
202
        rxpacket:       std_logic;      -- '1' when receiving a packet
203
        rxeep:          std_logic;      -- '1' when rx EEP character pending
204
        txpacket:       std_logic;      -- '1' when transmitting a packet
205
        txdiscard:      std_logic;      -- '1' when discarding a tx packet
206
        -- FIFO pointers
207
        rxfifo_raddr:   std_logic_vector(rxfifosize_bits-1 downto 0);
208
        rxfifo_waddr:   std_logic_vector(rxfifosize_bits-1 downto 0);
209
        txfifo_raddr:   std_logic_vector(txfifosize_bits-1 downto 0);
210
        txfifo_waddr:   std_logic_vector(txfifosize_bits-1 downto 0);
211
        -- FIFO state
212
        rxfifo_rvalid:  std_logic;      -- '1' if s_rxfifo_rdata is valid
213
        txfifo_rvalid:  std_logic;      -- '1' if s_txfifo_rdata is valid
214
        rxfull:         std_logic;      -- '1' if RX fifo is full
215
        rxhalff:        std_logic;      -- '1' if RX fifo is at least half full
216
        txfull:         std_logic;      -- '1' if TX fifo is full
217
        txhalff:        std_logic;      -- '1' if TX fifo is at least half full
218
        rxroom:         std_logic_vector(5 downto 0);
219
    end record;
220
 
221
    constant regs_reset: regs_type := (
222
        rxpacket        => '0',
223
        rxeep           => '0',
224
        txpacket        => '0',
225
        txdiscard       => '0',
226
        rxfifo_raddr    => (others => '0'),
227
        rxfifo_waddr    => (others => '0'),
228
        txfifo_raddr    => (others => '0'),
229
        txfifo_waddr    => (others => '0'),
230
        rxfifo_rvalid   => '0',
231
        txfifo_rvalid   => '0',
232
        rxfull          => '0',
233
        rxhalff         => '0',
234
        txfull          => '0',
235
        txhalff         => '0',
236
        rxroom          => (others => '0') );
237
 
238
    signal r: regs_type := regs_reset;
239
    signal rin: regs_type;
240
 
241
    -- Interface signals to components.
242
    signal recv_rxen:       std_logic;
243
    signal recvo:           spw_recv_out_type;
244
    signal recv_inact:      std_logic;
245
    signal recv_inbvalid:   std_logic;
246
    signal recv_inbits:     std_logic_vector(rxchunk-1 downto 0);
247
    signal xmiti:           spw_xmit_in_type;
248
    signal xmito:           spw_xmit_out_type;
249
    signal xmit_divcnt:     std_logic_vector(7 downto 0);
250
    signal linki:           spw_link_in_type;
251
    signal linko:           spw_link_out_type;
252
 
253
    -- Memory interface signals.
254
    signal s_rxfifo_raddr:  std_logic_vector(rxfifosize_bits-1 downto 0);
255
    signal s_rxfifo_rdata:  std_logic_vector(8 downto 0);
256
    signal s_rxfifo_wen:    std_logic;
257
    signal s_rxfifo_waddr:  std_logic_vector(rxfifosize_bits-1 downto 0);
258
    signal s_rxfifo_wdata:  std_logic_vector(8 downto 0);
259
    signal s_txfifo_raddr:  std_logic_vector(txfifosize_bits-1 downto 0);
260
    signal s_txfifo_rdata:  std_logic_vector(8 downto 0);
261
    signal s_txfifo_wen:    std_logic;
262
    signal s_txfifo_waddr:  std_logic_vector(txfifosize_bits-1 downto 0);
263
    signal s_txfifo_wdata:  std_logic_vector(8 downto 0);
264
 
265
begin
266
 
267
    -- Instantiate link controller.
268
    link_inst: spwlink
269
        generic map (
270
            reset_time  => reset_time )
271
        port map (
272
            clk         => clk,
273
            rst         => rst,
274
            linki       => linki,
275
            linko       => linko,
276
            rxen        => recv_rxen,
277
            recvo       => recvo,
278
            xmiti       => xmiti,
279
            xmito       => xmito );
280
 
281
    -- Instantiate receiver.
282
    recv_inst: spwrecv
283
        generic map(
284
            disconnect_time => disconnect_time,
285
            rxchunk     => rxchunk )
286
        port map (
287
            clk         => clk,
288
            rxen        => recv_rxen,
289
            recvo       => recvo,
290
            inact       => recv_inact,
291
            inbvalid    => recv_inbvalid,
292
            inbits      => recv_inbits );
293
 
294
    -- Instantiate transmitter.
295
    xmit_sel0: if tximpl = impl_generic generate
296
        xmit_inst: spwxmit
297
            port map (
298
                clk     => clk,
299
                rst     => rst,
300
                divcnt  => xmit_divcnt,
301
                xmiti   => xmiti,
302
                xmito   => xmito,
303
                spw_do  => spw_do,
304
                spw_so  => spw_so );
305
    end generate;
306
    xmit_sel1: if tximpl = impl_fast generate
307
        xmit_fast_inst: spwxmit_fast
308
            port map (
309
                clk     => clk,
310
                txclk   => txclk,
311
                rst     => rst,
312
                divcnt  => xmit_divcnt,
313
                xmiti   => xmiti,
314
                xmito   => xmito,
315
                spw_do  => spw_do,
316
                spw_so  => spw_so );
317
    end generate;
318
 
319
    -- Instantiate receiver front-end.
320
    recvfront_sel0: if rximpl = impl_generic generate
321
        recvfront_generic_inst: spwrecvfront_generic
322
            port map (
323
                clk         => clk,
324
                rxen        => recv_rxen,
325
                inact       => recv_inact,
326
                inbvalid    => recv_inbvalid,
327
                inbits      => recv_inbits,
328
                spw_di      => spw_di,
329
                spw_si      => spw_si );
330
    end generate;
331
    recvfront_sel1: if rximpl = impl_fast generate
332
        recvfront_fast_inst: spwrecvfront_fast
333
            generic map (
334
                rxchunk     => rxchunk )
335
            port map (
336
                clk         => clk,
337
                rxclk       => rxclk,
338
                rxen        => recv_rxen,
339
                inact       => recv_inact,
340
                inbvalid    => recv_inbvalid,
341
                inbits      => recv_inbits,
342
                spw_di      => spw_di,
343
                spw_si      => spw_si );
344
    end generate;
345
 
346
    -- Instantiate RX memory.
347
    rxmem: spwram
348
        generic map (
349
            abits       => rxfifosize_bits,
350
            dbits       => 9 )
351
        port map (
352
            rclk        => clk,
353
            wclk        => clk,
354
            ren         => '1',
355
            raddr       => s_rxfifo_raddr,
356
            rdata       => s_rxfifo_rdata,
357
            wen         => s_rxfifo_wen,
358
            waddr       => s_rxfifo_waddr,
359
            wdata       => s_rxfifo_wdata );
360
 
361
    -- Instantiate TX memory.
362
    txmem: spwram
363
        generic map (
364
            abits       => txfifosize_bits,
365
            dbits       => 9 )
366
        port map (
367
            rclk        => clk,
368
            wclk        => clk,
369
            ren         => '1',
370
            raddr       => s_txfifo_raddr,
371
            rdata       => s_txfifo_rdata,
372
            wen         => s_txfifo_wen,
373
            waddr       => s_txfifo_waddr,
374
            wdata       => s_txfifo_wdata );
375
 
376
    -- Combinatorial process
377
    process (r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread)  is
378
        variable v:             regs_type;
379
        variable v_tmprxroom:   unsigned(rxfifosize_bits-1 downto 0);
380
        variable v_tmptxroom:   unsigned(txfifosize_bits-1 downto 0);
381
    begin
382
        v           := r;
383
        v_tmprxroom := to_unsigned(0, v_tmprxroom'length);
384
        v_tmptxroom := to_unsigned(0, v_tmptxroom'length);
385
 
386
        -- Keep track of whether we are sending and/or receiving a packet.
387
        if linko.rxchar = '1' then
388
            -- got character
389
            v.rxpacket  := not linko.rxflag;
390
        end if;
391
        if linko.txack = '1' then
392
            -- send character
393
            v.txpacket  := not s_txfifo_rdata(8);
394
        end if;
395
        if linko.running = '0' then
396
            -- not connected
397
            v.rxpacket  := '0';
398
            v.txpacket  := '0';
399
        end if;
400
 
401
        -- Clear the discard flags when the link is explicitly disabled.
402
        if linkdis = '1' then
403
            v.rxeep     := '0';
404
            v.txdiscard := '0';
405
        end if;
406
 
407
        -- Update RX fifo pointers.
408
        if (rxread = '1') and (r.rxfifo_rvalid = '1') then
409
            -- read from fifo
410
            v.rxfifo_raddr  := std_logic_vector(unsigned(r.rxfifo_raddr) + 1);
411
        end if;
412
        if r.rxfull = '0' then
413
            if (linko.rxchar = '1') or (r.rxeep = '1') then
414
                -- write to fifo (received char or pending EEP)
415
                v.rxfifo_waddr  := std_logic_vector(unsigned(r.rxfifo_waddr) + 1);
416
            end if;
417
            v.rxeep         := '0';
418
        end if;
419
 
420
        -- Keep track of whether the RX fifo contains valid data.
421
        -- (use new value of rxfifo_raddr)
422
        v.rxfifo_rvalid := bool_to_logic(v.rxfifo_raddr /= r.rxfifo_waddr);
423
 
424
        -- Update room in RX fifo (use new value of rxfifo_waddr).
425
        v_tmprxroom := unsigned(r.rxfifo_raddr) - unsigned(v.rxfifo_waddr) - 1;
426
        v.rxfull    := bool_to_logic(v_tmprxroom = 0);
427
        v.rxhalff   := not v_tmprxroom(v_tmprxroom'high);
428
        if v_tmprxroom > 63 then
429
            v.rxroom    := (others => '1');
430
        else
431
            v.rxroom    := std_logic_vector(v_tmprxroom(5 downto 0));
432
        end if;
433
 
434
        -- Update TX fifo pointers.
435
        if (r.txfifo_rvalid = '1') and ((linko.txack = '1') or (r.txdiscard = '1')) then
436
            -- read from fifo
437
            v.txfifo_raddr  := std_logic_vector(unsigned(r.txfifo_raddr) + 1);
438
            if s_txfifo_rdata(8) = '1' then
439
                v.txdiscard := '0';     -- got EOP/EEP, stop discarding data
440
            end if;
441
        end if;
442
        if (r.txfull = '0') and (txwrite = '1') then
443
            -- write to fifo
444
            v.txfifo_waddr  := std_logic_vector(unsigned(r.txfifo_waddr) + 1);
445
        end if;
446
 
447
        -- Keep track of whether the TX fifo contains valid data.
448
        -- (use new value of txfifo_raddr)
449
        v.txfifo_rvalid := bool_to_logic(v.txfifo_raddr /= r.txfifo_waddr);
450
 
451
        -- Update room in TX fifo (use new value of both txfifo_waddr).
452
        v_tmptxroom := unsigned(r.txfifo_raddr) - unsigned(v.txfifo_waddr) - 1;
453
        v.txfull    := bool_to_logic(v_tmptxroom = 0);
454
        v.txhalff   := not v_tmptxroom(v_tmptxroom'high);
455
 
456
        -- If an error occurs, set a flag to discard the current packet.
457
        if (linko.errdisc or linko.errpar or
458
            linko.erresc or linko.errcred) = '1' then
459
            v.rxeep     := v.rxeep or v.rxpacket;   -- use new value of rxpacket
460
            v.txdiscard := v.txdiscard or r.txpacket;
461
            v.rxpacket  := '0';
462
            v.txpacket  := '0';
463
        end if;
464
 
465
        -- Drive control signals to RX fifo.
466
        s_rxfifo_raddr  <= v.rxfifo_raddr;  -- using new value of rxfifo_raddr
467
        s_rxfifo_wen    <= (not r.rxfull) and (linko.rxchar or r.rxeep);
468
        s_rxfifo_waddr  <= r.rxfifo_waddr;
469
        if r.rxeep = '1' then
470
            s_rxfifo_wdata  <= "100000001";
471
        else
472
            s_rxfifo_wdata  <= linko.rxflag & linko.rxdata;
473
        end if;
474
 
475
        -- Drive control signals to TX fifo.
476
        s_txfifo_raddr  <= v.txfifo_raddr;  -- using new value of txfifo_raddr
477
        s_txfifo_wen    <= (not r.txfull) and txwrite;
478
        s_txfifo_waddr  <= r.txfifo_waddr;
479
        s_txfifo_wdata  <= txflag & txdata;
480
 
481
        -- Drive inputs to spwlink.
482
        linki.autostart <= autostart;
483
        linki.linkstart <= linkstart;
484
        linki.linkdis   <= linkdis;
485
        linki.rxroom    <= r.rxroom;
486
        linki.tick_in   <= tick_in;
487
        linki.ctrl_in   <= ctrl_in;
488
        linki.time_in   <= time_in;
489
        linki.txwrite   <= r.txfifo_rvalid and not r.txdiscard;
490
        linki.txflag    <= s_txfifo_rdata(8);
491
        linki.txdata    <= s_txfifo_rdata(7 downto 0);
492
 
493
        -- Drive divcnt input to spwxmit.
494
        if linko.running = '1' then
495
            xmit_divcnt <= txdivcnt;
496
        else
497
            xmit_divcnt <= default_divcnt;
498
        end if;
499
 
500
        -- Drive outputs.
501
        txrdy       <= not r.txfull;
502
        txhalff     <= r.txhalff;
503
        tick_out    <= linko.tick_out;
504
        ctrl_out    <= linko.ctrl_out;
505
        time_out    <= linko.time_out;
506
        rxvalid     <= r.rxfifo_rvalid;
507
        rxhalff     <= r.rxhalff;
508
        rxflag      <= s_rxfifo_rdata(8);
509
        rxdata      <= s_rxfifo_rdata(7 downto 0);
510
        started     <= linko.started;
511
        connecting  <= linko.connecting;
512
        running     <= linko.running;
513
        errdisc     <= linko.errdisc;
514
        errpar      <= linko.errpar;
515
        erresc      <= linko.erresc;
516
        errcred     <= linko.errcred;
517
 
518
        -- Reset.
519
        if rst = '1' then
520
            v.rxpacket      := '0';
521
            v.rxeep         := '0';
522
            v.txpacket      := '0';
523
            v.txdiscard     := '0';
524
            v.rxfifo_raddr  := (others => '0');
525
            v.rxfifo_waddr  := (others => '0');
526
            v.txfifo_raddr  := (others => '0');
527
            v.txfifo_waddr  := (others => '0');
528
            v.rxfifo_rvalid := '0';
529
            v.txfifo_rvalid := '0';
530
        end if;
531
 
532
        -- Update registers.
533
        rin <= v;
534
    end process;
535
 
536
    -- Update registers.
537
    process (clk) is
538
    begin
539
        if rising_edge(clk) then
540
            r <= rin;
541
        end if;
542
    end process;
543
 
544
end architecture spwstream_arch;

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