OpenCores
URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwstream.vhd] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jorisvr
--
2
--  SpaceWire core with character-stream interface.
3
--
4
--  This entity provides a SpaceWire core with a character-stream interface.
5
--  The interface provides means for connection initiation, sending and
6
--  receiving of N-Chars and TimeCodes, and error reporting.
7
--
8
--  This entity instantiates spwlink, spwrecv, spwxmit and one of the
9
--  spwrecvfront implementations. It also implements a receive FIFO and
10
--  a transmit FIFO.
11
--
12
--  The SpaceWire standard requires that each transceiver use an initial
13
--  signalling rate of 10 Mbit/s. This implies that the system clock frequency
14 3 jorisvr
--  must be a multiple of 10 MHz. See the manual for further details on
15 2 jorisvr
--  bitrates and clocking.
16
--
17
 
18
library ieee;
19
use ieee.std_logic_1164.all;
20
use ieee.numeric_std.all;
21
use work.spwpkg.all;
22
 
23
entity spwstream is
24
 
25
    generic (
26
        -- System clock frequency in Hz.
27
        -- This must be set to the frequency of "clk". It is used to setup
28
        -- counters for reset timing, disconnect timeout and to transmit
29 3 jorisvr
        -- at 10 Mbit/s during the link handshake.
30 2 jorisvr
        sysfreq:        real;
31
 
32 3 jorisvr
        -- Transmit clock frequency in Hz (only if tximpl = impl_fast).
33
        -- This must be set to the frequency of "txclk". It is used to
34
        -- transmit at 10 Mbit/s during the link handshake.
35
        txclkfreq:      real := 0.0;
36
 
37 2 jorisvr
        -- Selection of a receiver front-end implementation.
38
        rximpl:         spw_implementation_type := impl_generic;
39
 
40
        -- Maximum number of bits received per system clock
41
        -- (must be 1 in case of impl_generic).
42
        rxchunk:        integer range 1 to 4 := 1;
43
 
44
        -- Selection of a transmitter implementation.
45
        tximpl:         spw_implementation_type := impl_generic;
46
 
47
        -- Size of the receive FIFO as the 2-logarithm of the number of bytes.
48
        -- Must be at least 6 (64 bytes).
49
        rxfifosize_bits: integer range 6 to 14 := 11;
50
 
51
        -- Size of the transmit FIFO as the 2-logarithm of the number of bytes.
52
        txfifosize_bits: integer range 2 to 14 := 11
53
    );
54
 
55
    port (
56
        -- System clock.
57
        clk:        in  std_logic;
58
 
59
        -- Receiver sample clock (only for impl_fast)
60
        rxclk:      in  std_logic;
61
 
62
        -- Transmit clock (only for impl_fast)
63
        txclk:      in  std_logic;
64
 
65
        -- Synchronous reset (active-high).
66
        rst:        in  std_logic;
67
 
68
        -- Enables automatic link start on receipt of a NULL character.
69
        autostart:  in  std_logic;
70
 
71
        -- Enables link start once the Ready state is reached.
72
        -- Without autostart or linkstart, the link remains in state Ready.
73
        linkstart:  in  std_logic;
74
 
75 3 jorisvr
        -- Do not start link (overrides linkstart and autostart) and/or
76
        -- disconnect a running link.
77 2 jorisvr
        linkdis:    in  std_logic;
78
 
79 3 jorisvr
        -- Scaling factor minus 1, used to scale the transmit base clock into
80
        -- the transmission bit rate. The system clock (for impl_generic) or
81
        -- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1).
82 2 jorisvr
        -- Changing this signal will immediately change the transmission rate.
83
        -- During link setup, the transmission rate is always 10 Mbit/s.
84
        txdivcnt:   in  std_logic_vector(7 downto 0);
85
 
86
        -- High for one clock cycle to request transmission of a TimeCode.
87
        -- The request is registered inside the entity until it can be processed.
88
        tick_in:    in  std_logic;
89
 
90
        -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
91
        ctrl_in:    in  std_logic_vector(1 downto 0);
92
 
93
        -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
94
        time_in:    in  std_logic_vector(5 downto 0);
95
 
96
        -- Pulled high by the application to write an N-Char to the transmit
97
        -- queue. If "txwrite" and "txrdy" are both high on the rising edge
98
        -- of "clk", a character is added to the transmit queue.
99
        -- This signal has no effect if "txrdy" is low.
100
        txwrite:    in  std_logic;
101
 
102
        -- Control flag to be sent with the next N_Char.
103
        -- Must be valid while txwrite is high.
104
        txflag:     in  std_logic;
105
 
106
        -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
107
        -- Must be valid while txwrite is high.
108
        txdata:     in  std_logic_vector(7 downto 0);
109
 
110
        -- High if the entity is ready to accept an N-Char for transmission.
111
        txrdy:      out std_logic;
112
 
113
        -- High if the transmission queue is at least half full.
114
        txhalff:    out std_logic;
115
 
116
        -- High for one clock cycle if a TimeCode was just received.
117
        tick_out:   out std_logic;
118
 
119
        -- Control bits of the last received TimeCode.
120
        ctrl_out:   out std_logic_vector(1 downto 0);
121
 
122
        -- Counter value of the last received TimeCode.
123
        time_out:   out std_logic_vector(5 downto 0);
124
 
125
        -- High if "rxflag" and "rxdata" contain valid data.
126
        -- This signal is high unless the receive FIFO is empty.
127
        rxvalid:    out std_logic;
128
 
129
        -- High if the receive FIFO is at least half full.
130
        rxhalff:    out std_logic;
131
 
132
        -- High if the received character is EOP or EEP; low if the received
133
        -- character is a data byte. Valid if "rxvalid" is high.
134
        rxflag:     out std_logic;
135
 
136
        -- Received byte, or "00000000" for EOP or "00000001" for EEP.
137
        -- Valid if "rxvalid" is high.
138
        rxdata:     out std_logic_vector(7 downto 0);
139
 
140
        -- Pulled high by the application to accept a received character.
141
        -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
142
        -- a character is removed from the receive FIFO and "rxvalid", "rxflag"
143
        -- and "rxdata" are updated.
144
        -- This signal has no effect if "rxvalid" is low.
145
        rxread:     in  std_logic;
146
 
147
        -- High if the link state machine is currently in the Started state.
148
        started:    out std_logic;
149
 
150
        -- High if the link state machine is currently in the Connecting state.
151
        connecting: out std_logic;
152
 
153
        -- High if the link state machine is currently in the Run state, indicating
154
        -- that the link is fully operational. If none of started, connecting or running
155
        -- is high, the link is in an initial state and the transmitter is not yet enabled.
156
        running:    out std_logic;
157
 
158
        -- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
159
        -- This indication is auto-clearing.
160
        errdisc:    out std_logic;
161
 
162
        -- Parity error detected in state Run. Triggers a reset and reconnect of the link.
163
        -- This indication is auto-clearing.
164
        errpar:     out std_logic;
165
 
166
        -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
167
        -- the link. This indication is auto-clearing.
168
        erresc:     out std_logic;
169
 
170
        -- Credit error detected. Triggers a reset and reconnect of the link.
171
        -- This indication is auto-clearing.
172
        errcred:    out std_logic;
173
 
174
        -- Data In signal from SpaceWire bus.
175
        spw_di:     in  std_logic;
176
 
177
        -- Strobe In signal from SpaceWire bus.
178
        spw_si:     in  std_logic;
179
 
180
        -- Data Out signal to SpaceWire bus.
181
        spw_do:     out std_logic;
182
 
183
        -- Strobe Out signal to SpaceWire bus.
184
        spw_so:     out std_logic
185
    );
186
 
187
end entity spwstream;
188
 
189
architecture spwstream_arch of spwstream is
190
 
191
    -- Convert boolean to std_logic.
192
    type bool_to_logic_type is array(boolean) of std_ulogic;
193
    constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
194
 
195
    -- Reset time (6.4 us) in system clocks
196
    constant reset_time:        integer := integer(sysfreq * 6.4e-6);
197
 
198
    -- Disconnect time (850 ns) in system clocks
199
    constant disconnect_time:   integer := integer(sysfreq * 850.0e-9);
200
 
201
    -- Initial tx clock scaler (10 Mbit).
202 3 jorisvr
    type impl_to_real_type is array(spw_implementation_type) of real;
203
    constant tximpl_to_txclk_freq: impl_to_real_type :=
204
        (impl_generic => sysfreq, impl_fast => txclkfreq);
205
    constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl);
206 2 jorisvr
    constant default_divcnt:    std_logic_vector(7 downto 0) :=
207 3 jorisvr
        std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8));
208 2 jorisvr
 
209
    -- Registers.
210
    type regs_type is record
211
        -- packet state
212
        rxpacket:       std_logic;      -- '1' when receiving a packet
213
        rxeep:          std_logic;      -- '1' when rx EEP character pending
214
        txpacket:       std_logic;      -- '1' when transmitting a packet
215
        txdiscard:      std_logic;      -- '1' when discarding a tx packet
216
        -- FIFO pointers
217
        rxfifo_raddr:   std_logic_vector(rxfifosize_bits-1 downto 0);
218
        rxfifo_waddr:   std_logic_vector(rxfifosize_bits-1 downto 0);
219
        txfifo_raddr:   std_logic_vector(txfifosize_bits-1 downto 0);
220
        txfifo_waddr:   std_logic_vector(txfifosize_bits-1 downto 0);
221
        -- FIFO state
222
        rxfifo_rvalid:  std_logic;      -- '1' if s_rxfifo_rdata is valid
223
        txfifo_rvalid:  std_logic;      -- '1' if s_txfifo_rdata is valid
224
        rxfull:         std_logic;      -- '1' if RX fifo is full
225
        rxhalff:        std_logic;      -- '1' if RX fifo is at least half full
226
        txfull:         std_logic;      -- '1' if TX fifo is full
227
        txhalff:        std_logic;      -- '1' if TX fifo is at least half full
228
        rxroom:         std_logic_vector(5 downto 0);
229
    end record;
230
 
231
    constant regs_reset: regs_type := (
232
        rxpacket        => '0',
233
        rxeep           => '0',
234
        txpacket        => '0',
235
        txdiscard       => '0',
236
        rxfifo_raddr    => (others => '0'),
237
        rxfifo_waddr    => (others => '0'),
238
        txfifo_raddr    => (others => '0'),
239
        txfifo_waddr    => (others => '0'),
240
        rxfifo_rvalid   => '0',
241
        txfifo_rvalid   => '0',
242
        rxfull          => '0',
243
        rxhalff         => '0',
244
        txfull          => '0',
245
        txhalff         => '0',
246
        rxroom          => (others => '0') );
247
 
248
    signal r: regs_type := regs_reset;
249
    signal rin: regs_type;
250
 
251
    -- Interface signals to components.
252
    signal recv_rxen:       std_logic;
253
    signal recvo:           spw_recv_out_type;
254
    signal recv_inact:      std_logic;
255
    signal recv_inbvalid:   std_logic;
256
    signal recv_inbits:     std_logic_vector(rxchunk-1 downto 0);
257
    signal xmiti:           spw_xmit_in_type;
258
    signal xmito:           spw_xmit_out_type;
259
    signal xmit_divcnt:     std_logic_vector(7 downto 0);
260
    signal linki:           spw_link_in_type;
261
    signal linko:           spw_link_out_type;
262
 
263
    -- Memory interface signals.
264
    signal s_rxfifo_raddr:  std_logic_vector(rxfifosize_bits-1 downto 0);
265
    signal s_rxfifo_rdata:  std_logic_vector(8 downto 0);
266
    signal s_rxfifo_wen:    std_logic;
267
    signal s_rxfifo_waddr:  std_logic_vector(rxfifosize_bits-1 downto 0);
268
    signal s_rxfifo_wdata:  std_logic_vector(8 downto 0);
269
    signal s_txfifo_raddr:  std_logic_vector(txfifosize_bits-1 downto 0);
270
    signal s_txfifo_rdata:  std_logic_vector(8 downto 0);
271
    signal s_txfifo_wen:    std_logic;
272
    signal s_txfifo_waddr:  std_logic_vector(txfifosize_bits-1 downto 0);
273
    signal s_txfifo_wdata:  std_logic_vector(8 downto 0);
274
 
275
begin
276
 
277
    -- Instantiate link controller.
278
    link_inst: spwlink
279
        generic map (
280
            reset_time  => reset_time )
281
        port map (
282
            clk         => clk,
283
            rst         => rst,
284
            linki       => linki,
285
            linko       => linko,
286
            rxen        => recv_rxen,
287
            recvo       => recvo,
288
            xmiti       => xmiti,
289
            xmito       => xmito );
290
 
291
    -- Instantiate receiver.
292
    recv_inst: spwrecv
293
        generic map(
294
            disconnect_time => disconnect_time,
295
            rxchunk     => rxchunk )
296
        port map (
297
            clk         => clk,
298
            rxen        => recv_rxen,
299
            recvo       => recvo,
300
            inact       => recv_inact,
301
            inbvalid    => recv_inbvalid,
302
            inbits      => recv_inbits );
303
 
304
    -- Instantiate transmitter.
305
    xmit_sel0: if tximpl = impl_generic generate
306
        xmit_inst: spwxmit
307
            port map (
308
                clk     => clk,
309
                rst     => rst,
310
                divcnt  => xmit_divcnt,
311
                xmiti   => xmiti,
312
                xmito   => xmito,
313
                spw_do  => spw_do,
314
                spw_so  => spw_so );
315
    end generate;
316
    xmit_sel1: if tximpl = impl_fast generate
317
        xmit_fast_inst: spwxmit_fast
318
            port map (
319
                clk     => clk,
320
                txclk   => txclk,
321
                rst     => rst,
322
                divcnt  => xmit_divcnt,
323
                xmiti   => xmiti,
324
                xmito   => xmito,
325
                spw_do  => spw_do,
326
                spw_so  => spw_so );
327
    end generate;
328
 
329
    -- Instantiate receiver front-end.
330
    recvfront_sel0: if rximpl = impl_generic generate
331
        recvfront_generic_inst: spwrecvfront_generic
332
            port map (
333
                clk         => clk,
334
                rxen        => recv_rxen,
335
                inact       => recv_inact,
336
                inbvalid    => recv_inbvalid,
337
                inbits      => recv_inbits,
338
                spw_di      => spw_di,
339
                spw_si      => spw_si );
340
    end generate;
341
    recvfront_sel1: if rximpl = impl_fast generate
342
        recvfront_fast_inst: spwrecvfront_fast
343
            generic map (
344
                rxchunk     => rxchunk )
345
            port map (
346
                clk         => clk,
347
                rxclk       => rxclk,
348
                rxen        => recv_rxen,
349
                inact       => recv_inact,
350
                inbvalid    => recv_inbvalid,
351
                inbits      => recv_inbits,
352
                spw_di      => spw_di,
353
                spw_si      => spw_si );
354
    end generate;
355
 
356
    -- Instantiate RX memory.
357
    rxmem: spwram
358
        generic map (
359
            abits       => rxfifosize_bits,
360
            dbits       => 9 )
361
        port map (
362
            rclk        => clk,
363
            wclk        => clk,
364
            ren         => '1',
365
            raddr       => s_rxfifo_raddr,
366
            rdata       => s_rxfifo_rdata,
367
            wen         => s_rxfifo_wen,
368
            waddr       => s_rxfifo_waddr,
369
            wdata       => s_rxfifo_wdata );
370
 
371
    -- Instantiate TX memory.
372
    txmem: spwram
373
        generic map (
374
            abits       => txfifosize_bits,
375
            dbits       => 9 )
376
        port map (
377
            rclk        => clk,
378
            wclk        => clk,
379
            ren         => '1',
380
            raddr       => s_txfifo_raddr,
381
            rdata       => s_txfifo_rdata,
382
            wen         => s_txfifo_wen,
383
            waddr       => s_txfifo_waddr,
384
            wdata       => s_txfifo_wdata );
385
 
386
    -- Combinatorial process
387
    process (r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread)  is
388
        variable v:             regs_type;
389
        variable v_tmprxroom:   unsigned(rxfifosize_bits-1 downto 0);
390
        variable v_tmptxroom:   unsigned(txfifosize_bits-1 downto 0);
391
    begin
392
        v           := r;
393
        v_tmprxroom := to_unsigned(0, v_tmprxroom'length);
394
        v_tmptxroom := to_unsigned(0, v_tmptxroom'length);
395
 
396
        -- Keep track of whether we are sending and/or receiving a packet.
397
        if linko.rxchar = '1' then
398
            -- got character
399
            v.rxpacket  := not linko.rxflag;
400
        end if;
401
        if linko.txack = '1' then
402
            -- send character
403
            v.txpacket  := not s_txfifo_rdata(8);
404
        end if;
405
 
406
        -- Update RX fifo pointers.
407
        if (rxread = '1') and (r.rxfifo_rvalid = '1') then
408
            -- read from fifo
409
            v.rxfifo_raddr  := std_logic_vector(unsigned(r.rxfifo_raddr) + 1);
410
        end if;
411
        if r.rxfull = '0' then
412
            if (linko.rxchar = '1') or (r.rxeep = '1') then
413
                -- write to fifo (received char or pending EEP)
414
                v.rxfifo_waddr  := std_logic_vector(unsigned(r.rxfifo_waddr) + 1);
415
            end if;
416
            v.rxeep         := '0';
417
        end if;
418
 
419
        -- Keep track of whether the RX fifo contains valid data.
420
        -- (use new value of rxfifo_raddr)
421
        v.rxfifo_rvalid := bool_to_logic(v.rxfifo_raddr /= r.rxfifo_waddr);
422
 
423
        -- Update room in RX fifo (use new value of rxfifo_waddr).
424
        v_tmprxroom := unsigned(r.rxfifo_raddr) - unsigned(v.rxfifo_waddr) - 1;
425
        v.rxfull    := bool_to_logic(v_tmprxroom = 0);
426
        v.rxhalff   := not v_tmprxroom(v_tmprxroom'high);
427
        if v_tmprxroom > 63 then
428
            v.rxroom    := (others => '1');
429
        else
430
            v.rxroom    := std_logic_vector(v_tmprxroom(5 downto 0));
431
        end if;
432
 
433
        -- Update TX fifo pointers.
434
        if (r.txfifo_rvalid = '1') and ((linko.txack = '1') or (r.txdiscard = '1')) then
435
            -- read from fifo
436
            v.txfifo_raddr  := std_logic_vector(unsigned(r.txfifo_raddr) + 1);
437
            if s_txfifo_rdata(8) = '1' then
438
                v.txdiscard := '0';     -- got EOP/EEP, stop discarding data
439
            end if;
440
        end if;
441
        if (r.txfull = '0') and (txwrite = '1') then
442
            -- write to fifo
443
            v.txfifo_waddr  := std_logic_vector(unsigned(r.txfifo_waddr) + 1);
444
        end if;
445
 
446
        -- Keep track of whether the TX fifo contains valid data.
447
        -- (use new value of txfifo_raddr)
448
        v.txfifo_rvalid := bool_to_logic(v.txfifo_raddr /= r.txfifo_waddr);
449
 
450 4 jorisvr
        -- Update room in TX fifo (use new value of txfifo_waddr).
451 2 jorisvr
        v_tmptxroom := unsigned(r.txfifo_raddr) - unsigned(v.txfifo_waddr) - 1;
452
        v.txfull    := bool_to_logic(v_tmptxroom = 0);
453
        v.txhalff   := not v_tmptxroom(v_tmptxroom'high);
454
 
455 5 jorisvr
        -- If the link is lost, set a flag to discard the current packet.
456
        if linko.running = '0' then
457 4 jorisvr
            v.rxeep     := v.rxeep or v.rxpacket;       -- use new value of rxpacket
458
            v.txdiscard := v.txdiscard or v.txpacket;   -- use new value of txpacket
459 2 jorisvr
            v.rxpacket  := '0';
460
            v.txpacket  := '0';
461
        end if;
462
 
463 5 jorisvr
        -- Clear the discard flag when the link is explicitly disabled.
464
        if linkdis = '1' then
465
            v.txdiscard := '0';
466
        end if;
467
 
468 2 jorisvr
        -- Drive control signals to RX fifo.
469
        s_rxfifo_raddr  <= v.rxfifo_raddr;  -- using new value of rxfifo_raddr
470
        s_rxfifo_wen    <= (not r.rxfull) and (linko.rxchar or r.rxeep);
471
        s_rxfifo_waddr  <= r.rxfifo_waddr;
472
        if r.rxeep = '1' then
473
            s_rxfifo_wdata  <= "100000001";
474
        else
475
            s_rxfifo_wdata  <= linko.rxflag & linko.rxdata;
476
        end if;
477
 
478
        -- Drive control signals to TX fifo.
479
        s_txfifo_raddr  <= v.txfifo_raddr;  -- using new value of txfifo_raddr
480
        s_txfifo_wen    <= (not r.txfull) and txwrite;
481
        s_txfifo_waddr  <= r.txfifo_waddr;
482
        s_txfifo_wdata  <= txflag & txdata;
483
 
484
        -- Drive inputs to spwlink.
485
        linki.autostart <= autostart;
486
        linki.linkstart <= linkstart;
487
        linki.linkdis   <= linkdis;
488
        linki.rxroom    <= r.rxroom;
489
        linki.tick_in   <= tick_in;
490
        linki.ctrl_in   <= ctrl_in;
491
        linki.time_in   <= time_in;
492
        linki.txwrite   <= r.txfifo_rvalid and not r.txdiscard;
493
        linki.txflag    <= s_txfifo_rdata(8);
494
        linki.txdata    <= s_txfifo_rdata(7 downto 0);
495
 
496
        -- Drive divcnt input to spwxmit.
497
        if linko.running = '1' then
498
            xmit_divcnt <= txdivcnt;
499
        else
500
            xmit_divcnt <= default_divcnt;
501
        end if;
502
 
503
        -- Drive outputs.
504
        txrdy       <= not r.txfull;
505
        txhalff     <= r.txhalff;
506
        tick_out    <= linko.tick_out;
507
        ctrl_out    <= linko.ctrl_out;
508
        time_out    <= linko.time_out;
509
        rxvalid     <= r.rxfifo_rvalid;
510
        rxhalff     <= r.rxhalff;
511
        rxflag      <= s_rxfifo_rdata(8);
512
        rxdata      <= s_rxfifo_rdata(7 downto 0);
513
        started     <= linko.started;
514
        connecting  <= linko.connecting;
515
        running     <= linko.running;
516
        errdisc     <= linko.errdisc;
517
        errpar      <= linko.errpar;
518
        erresc      <= linko.erresc;
519
        errcred     <= linko.errcred;
520
 
521
        -- Reset.
522
        if rst = '1' then
523
            v.rxpacket      := '0';
524
            v.rxeep         := '0';
525
            v.txpacket      := '0';
526
            v.txdiscard     := '0';
527
            v.rxfifo_raddr  := (others => '0');
528
            v.rxfifo_waddr  := (others => '0');
529
            v.txfifo_raddr  := (others => '0');
530
            v.txfifo_waddr  := (others => '0');
531
            v.rxfifo_rvalid := '0';
532
            v.txfifo_rvalid := '0';
533
        end if;
534
 
535
        -- Update registers.
536
        rin <= v;
537
    end process;
538
 
539
    -- Update registers.
540
    process (clk) is
541
    begin
542
        if rising_edge(clk) then
543
            r <= rin;
544
        end if;
545
    end process;
546
 
547
end architecture spwstream_arch;

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.