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[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [syncdff.vhd] - Blame information for rev 7

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1 7 jorisvr
--
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--  Double flip-flop synchronizer.
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--
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--  This entity is used to safely capture asynchronous signals.
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--
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--  An implementation may assign additional constraints to this entity
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--  in order to reduce the probability of meta-stability issues.
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--  For example, an extra tight timing constraint could be placed on
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--  the data path from syncdff_ff1 to syncdff_ff2 to ensure that
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--  meta-stability of ff1 is resolved before ff2 captures the signal.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity syncdff is
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    port (
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        clk:        in  std_logic;          -- clock (destination domain)
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        rst:        in  std_logic;          -- asynchronous reset, active-high
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        di:         in  std_logic;          -- input data
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        do:         out std_logic           -- output data
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    );
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    -- Turn off register replication in XST.
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    attribute REGISTER_DUPLICATION: string;
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    attribute REGISTER_DUPLICATION of syncdff: entity is "NO";
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end entity syncdff;
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architecture syncdff_arch of syncdff is
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    -- flip-flops
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    signal syncdff_ff1: std_ulogic := '0';
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    signal syncdff_ff2: std_ulogic := '0';
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    -- Turn of shift-register extraction in XST.
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    attribute SHIFT_EXTRACT: string;
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    attribute SHIFT_EXTRACT of syncdff_ff1: signal is "NO";
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    attribute SHIFT_EXTRACT of syncdff_ff2: signal is "NO";
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    -- Tell XST to place both flip-flops in the same slice.
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    attribute RLOC: string;
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    attribute RLOC of syncdff_ff1: signal is "X0Y0";
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    attribute RLOC of syncdff_ff2: signal is "X0Y0";
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    -- Tell XST to keep the flip-flop net names to be used in timing constraints.
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    attribute KEEP: string;
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    attribute KEEP of syncdff_ff1: signal is "SOFT";
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    attribute KEEP of syncdff_ff2: signal is "SOFT";
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begin
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    -- second flip-flop drives the output signal
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    do <= syncdff_ff2;
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    process (clk, rst) is
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    begin
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        if rst = '1' then
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            -- asynchronous reset
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            syncdff_ff1 <= '0';
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            syncdff_ff2 <= '0';
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        elsif rising_edge(clk) then
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            -- data synchronization
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            syncdff_ff1 <= di;
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            syncdff_ff2 <= syncdff_ff1;
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        end if;
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    end process;
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end architecture syncdff_arch;

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