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1 5 jorisvr
-----------------------------------------------------------------------------
2
--  LEON3 Demonstration design
3
--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4
--
5
--  Modified by Joris van Rantwijk for use with SpaceWire Light.
6
------------------------------------------------------------------------------
7
--  This program is free software; you can redistribute it and/or modify
8
--  it under the terms of the GNU General Public License as published by
9
--  the Free Software Foundation; either version 2 of the License, or
10
--  (at your option) any later version.
11
--
12
--  This program is distributed in the hope that it will be useful,
13
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
14
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
--  GNU General Public License for more details.
16
--
17
--  You should have received a copy of the GNU General Public License
18
--  along with this program; if not, write to the Free Software
19
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
20
------------------------------------------------------------------------------
21
 
22
 
23
library ieee;
24
use ieee.std_logic_1164.all;
25
library grlib, techmap;
26
use grlib.amba.all;
27
use grlib.stdlib.all;
28
use techmap.gencomp.all;
29
library gaisler;
30
use gaisler.memctrl.all;
31
use gaisler.leon3.all;
32
use gaisler.uart.all;
33
use gaisler.misc.all;
34
use gaisler.can.all;
35
use gaisler.net.all;
36
use gaisler.jtag.all;
37
use gaisler.spacewire.all;
38
use gaisler.grusb.all;
39
use gaisler.ata.all;
40
 
41
library esa;
42
use esa.memoryctrl.all;
43
 
44
library unisim;
45
use unisim.vcomponents.DCM;
46
 
47
use work.config.all;
48 6 jorisvr
 
49
-- These statements are used in case SpaceWire Light is synthesized locally,
50
-- separate from the rest of GRLIB.
51 5 jorisvr
use work.spwpkg.all;
52
use work.spwambapkg.all;
53 6 jorisvr
---- The following statements should be used instead if SpaceWire Light
54
---- has been integrated into GRLIB.
55
-- library opencores;
56
-- use opencores.spwpkg.all;
57
-- use opencores.spwambapkg.all;
58 5 jorisvr
 
59
entity leon3mp is
60
  generic (
61
    fabtech       : integer := CFG_FABTECH;
62
    memtech       : integer := CFG_MEMTECH;
63
    padtech       : integer := CFG_PADTECH;
64
    clktech       : integer := CFG_CLKTECH;
65
    disas         : integer := CFG_DISAS;       -- Enable disassembly to console
66
    dbguart       : integer := CFG_DUART;       -- Print UART on console
67
    pclow         : integer := CFG_PCLOW
68
  );
69
  port (
70
    resetn        : in  std_ulogic;
71
    clk           : in  std_ulogic;     -- 50 MHz main clock
72
    clk3          : in  std_ulogic;     -- 25 MHz ethernet clock
73
    pllref        : in  std_ulogic;
74
    errorn        : out std_ulogic;
75
    wdogn         : out std_ulogic;
76
    address       : out std_logic_vector(27 downto 0);
77
    data          : inout std_logic_vector(31 downto 0);
78
    ramsn         : out std_logic_vector (4 downto 0);
79
    ramoen        : out std_logic_vector (4 downto 0);
80
    rwen          : out std_logic_vector (3 downto 0);
81
    oen           : out std_ulogic;
82
    writen        : out std_ulogic;
83
    read          : out std_ulogic;
84
    iosn          : out std_ulogic;
85
    bexcn         : in  std_ulogic;                     -- DSU rx data
86
    brdyn         : in  std_ulogic;                     -- DSU rx data
87
    romsn         : out std_logic_vector (1 downto 0);
88
    sdclk         : out std_ulogic;
89
    sdcsn         : out std_logic_vector (1 downto 0);    -- sdram chip select
90
    sdwen         : out std_ulogic;                       -- sdram write enable
91
    sdrasn        : out std_ulogic;                       -- sdram ras
92
    sdcasn        : out std_ulogic;                       -- sdram cas
93
    sddqm         : out std_logic_vector (3 downto 0);    -- sdram dqm
94
 
95
    dsuen         : in std_ulogic;
96
    dsubre        : in std_ulogic;
97
    dsuact        : out std_ulogic;
98
 
99
    txd1          : out std_ulogic;                     -- UART1 tx data
100
    rxd1          : in  std_ulogic;                     -- UART1 rx data
101
    ctsn1         : in  std_ulogic;                     -- UART1 rx data
102
    rtsn1         : out std_ulogic;                     -- UART1 rx data
103
    txd2          : out std_ulogic;                     -- UART2 tx data
104
    rxd2          : in  std_ulogic;                     -- UART2 rx data
105
    ctsn2         : in  std_ulogic;                     -- UART1 rx data
106
    rtsn2         : out std_ulogic;                     -- UART1 rx data
107
 
108
    pio           : inout std_logic_vector(17 downto 0);         -- I/O port
109
 
110
    emdio         : inout std_logic;            -- ethernet PHY interface
111
    etx_clk       : in std_ulogic;
112
    erx_clk       : in std_ulogic;
113
    erxd          : in std_logic_vector(3 downto 0);
114
    erx_dv        : in std_ulogic;
115
    erx_er        : in std_ulogic;
116
    erx_col       : in std_ulogic;
117
    erx_crs       : in std_ulogic;
118
    emdint        : in std_ulogic;
119
    etxd          : out std_logic_vector(3 downto 0);
120
    etx_en        : out std_ulogic;
121
    etx_er        : out std_ulogic;
122
    emdc          : out std_ulogic;
123
 
124
    ps2clk        : inout std_logic_vector(1 downto 0);
125
    ps2data       : inout std_logic_vector(1 downto 0);
126
 
127
    vid_clock     : out std_ulogic;
128
    vid_blankn    : out std_ulogic;
129
    vid_syncn     : out std_ulogic;
130
    vid_hsync     : out std_ulogic;
131
    vid_vsync     : out std_ulogic;
132
    vid_r         : out std_logic_vector(7 downto 0);
133
    vid_g         : out std_logic_vector(7 downto 0);
134
    vid_b         : out std_logic_vector(7 downto 0);
135
 
136
    spw_clk       : in  std_ulogic;
137
    spw_rxdp      : in  std_logic_vector(0 to 2);
138
    spw_rxdn      : in  std_logic_vector(0 to 2);
139
    spw_rxsp      : in  std_logic_vector(0 to 2);
140
    spw_rxsn      : in  std_logic_vector(0 to 2);
141
    spw_txdp      : out std_logic_vector(0 to 2);
142
    spw_txdn      : out std_logic_vector(0 to 2);
143
    spw_txsp      : out std_logic_vector(0 to 2);
144
    spw_txsn      : out std_logic_vector(0 to 2);
145
 
146
    usb_clkout    : in std_ulogic;
147
    usb_d         : inout std_logic_vector(15 downto 0);
148
    usb_linestate : in std_logic_vector(1 downto 0);
149
    usb_opmode    : out std_logic_vector(1 downto 0);
150
    usb_reset     : out std_ulogic;
151
    usb_rxactive  : in std_ulogic;
152
    usb_rxerror   : in std_ulogic;
153
    usb_rxvalid   : in std_ulogic;
154
    usb_suspend   : out std_ulogic;
155
    usb_termsel   : out std_ulogic;
156
    usb_txready   : in std_ulogic;
157
    usb_txvalid   : out std_ulogic;
158
    usb_validh    : inout std_ulogic;
159
    usb_xcvrsel   : out std_ulogic;
160
    usb_vbus      : in std_ulogic;
161
 
162
    ata_rstn  : out std_logic;
163
    ata_data  : inout std_logic_vector(15 downto 0);
164
    ata_da    : out std_logic_vector(2 downto 0);
165
    ata_cs0   : out std_logic;
166
    ata_cs1   : out std_logic;
167
    ata_dior  : out std_logic;
168
    ata_diow  : out std_logic;
169
    ata_iordy : in std_logic;
170
    ata_intrq : in std_logic;
171
    ata_dmarq : in std_logic;
172
    ata_dmack : out std_logic;
173
    --ata_dasp  : in std_logic
174
    ata_csel  : out std_logic
175
 
176
        );
177
end;
178
 
179
architecture rtl of leon3mp is
180
 
181
attribute syn_netlist_hierarchy : boolean;
182
attribute syn_netlist_hierarchy of rtl : architecture is false;
183
 
184
constant blength : integer := 12;
185
constant fifodepth : integer := 8;
186
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
187
        CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
188
        CFG_ATA+CFG_GRUSBDC;
189
 
190
signal vcc, gnd   : std_logic_vector(4 downto 0);
191
signal memi  : memory_in_type;
192
signal memo  : memory_out_type;
193
signal wpo   : wprot_out_type;
194
signal sdi   : sdctrl_in_type;
195
signal sdo   : sdram_out_type;
196
signal sdo2, sdo3 : sdctrl_out_type;
197
 
198
signal apbi  : apb_slv_in_type;
199
signal apbo  : apb_slv_out_vector := (others => apb_none);
200
signal ahbsi : ahb_slv_in_type;
201
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
202
signal ahbmi : ahb_mst_in_type;
203
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
204
 
205
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
206
signal cgi, cgi2   : clkgen_in_type;
207
signal cgo, cgo2   : clkgen_out_type;
208
signal u1i, u2i, dui : uart_in_type;
209
signal u1o, u2o, duo : uart_out_type;
210
 
211
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
212
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
213
 
214
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
215
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
216
 
217
signal dsui : dsu_in_type;
218
signal dsuo : dsu_out_type;
219
 
220
signal ethi, ethi1, ethi2 : eth_in_type;
221
signal etho, etho1, etho2 : eth_out_type;
222
 
223
signal gpti : gptimer_in_type;
224
signal gpto : gptimer_out_type;
225
 
226
signal gpioi : gpio_in_type;
227
signal gpioo : gpio_out_type;
228
 
229
signal can_lrx, can_ltx   : std_logic_vector(0 to 7);
230
 
231
signal lclk, rst, ndsuact, wdogl : std_ulogic;
232
signal tck, tckn, tms, tdi, tdo : std_ulogic;
233
 
234
signal ethclk : std_ulogic;
235
 
236
signal kbdi  : ps2_in_type;
237
signal kbdo  : ps2_out_type;
238
signal moui  : ps2_in_type;
239
signal mouo  : ps2_out_type;
240
signal vgao  : apbvga_out_type;
241
 
242
constant BOARD_FREQ : integer := 50000;   -- input frequency in KHz
243
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;  -- cpu frequency in KHz
244
constant IOAEN : integer := CFG_CAN + CFG_ATA + CFG_GRUSBDC;
245
 
246
signal stati : ahbstat_in_type;
247
 
248
signal spw_clkl   : std_ulogic;
249
signal spw_tick_in: std_logic;
250
signal spw_di: std_logic;
251
signal spw_si: std_logic;
252
signal spw_do: std_logic;
253
signal spw_so: std_logic;
254
 
255
signal uclk : std_ulogic;
256
signal usbi : grusb_in_type;
257
signal usbo : grusb_out_type;
258
 
259
signal idei : ata_in_type;
260
signal ideo : ata_out_type;
261
 
262
constant SPW_LOOP_BACK : integer := 0;
263
 
264
signal dac_clk, video_clk, clk50 : std_logic;  -- signals to vga_clkgen.
265
signal clk_sel : std_logic_vector(1 downto 0);
266
 
267
attribute keep : boolean;
268
attribute syn_keep : boolean;
269
attribute syn_preserve : boolean;
270
attribute syn_keep of clk50 : signal is true;
271
attribute syn_preserve of clk50 : signal is true;
272
attribute keep of clk50 : signal is true;
273
attribute syn_keep of video_clk : signal is true;
274
attribute syn_preserve of video_clk : signal is true;
275
attribute keep of video_clk : signal is true;
276
attribute keep of spw_clkl : signal is true;
277
 
278
begin
279
 
280
----------------------------------------------------------------------
281
---  Reset and Clock generation  -------------------------------------
282
----------------------------------------------------------------------
283
 
284
  vcc <= (others => '1'); gnd <= (others => '0');
285
  cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
286
 
287
  pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
288
  ethclk_pad : inpad generic map (tech => padtech) port map(clk3, ethclk);
289
  clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
290
  clkgen0 : clkgen              -- clock generator
291
    generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
292
        CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
293
    port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50);
294
 
295
  sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
296
        port map (sdclk, sdclkl);
297
 
298
  resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
299
  rst0 : rstgen                 -- reset generator
300
  port map (rst, clkm, cgo.clklock, rstn, rstraw);
301
 
302
----------------------------------------------------------------------
303
---  AHB CONTROLLER --------------------------------------------------
304
----------------------------------------------------------------------
305
 
306
  ahb0 : ahbctrl                -- AHB arbiter/multiplexer
307
  generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
308
        rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
309
        ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
310
  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
311
 
312
----------------------------------------------------------------------
313
---  LEON3 processor and DSU -----------------------------------------
314
----------------------------------------------------------------------
315
 
316
  l3 : if CFG_LEON3 = 1 generate
317
    cpu : for i in 0 to CFG_NCPU-1 generate
318
      u0 : leon3s                       -- LEON3 processor      
319
      generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
320
        0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
321
        CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
322
        CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
323
        CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
324
        CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
325
        CFG_MMU_PAGE, CFG_BP)
326
      port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
327
                irqi(i), irqo(i), dbgi(i), dbgo(i));
328
    end generate;
329
    errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
330
 
331
    dsugen : if CFG_DSU = 1 generate
332
      dsu0 : dsu3                       -- LEON3 Debug Support Unit
333
      generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
334
         ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
335
      port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
336
      dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
337
      dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
338
      dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
339
      ndsuact <= not dsuo.active;
340
    end generate;
341
  end generate;
342
  nodsu : if CFG_DSU = 0 generate
343
    dsuo.tstop <= '0'; dsuo.active <= '0';
344
  end generate;
345
 
346
  dcomgen : if CFG_AHB_UART = 1 generate
347
    dcom0: ahbuart              -- Debug UART
348
    generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
349
    port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
350
    dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
351
    dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
352
  end generate;
353
  nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
354
 
355
  ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
356
    ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
357
      port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
358
               open, open, open, open, open, open, open, gnd(0));
359
  end generate;
360
 
361
----------------------------------------------------------------------
362
---  Memory controllers ----------------------------------------------
363
----------------------------------------------------------------------
364
 
365
  memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
366
  brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
367
  bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
368
 
369
  mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
370
        paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
371
        ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
372
        invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
373
        pageburst => CFG_MCTRL_PAGE)
374
  port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
375
  sdpads : if CFG_MCTRL_SDEN = 1 generate               -- SDRAM controller
376
      sdwen_pad : outpad generic map (tech => padtech)
377
           port map (sdwen, sdo.sdwen);
378
      sdras_pad : outpad generic map (tech => padtech)
379
           port map (sdrasn, sdo.rasn);
380
      sdcas_pad : outpad generic map (tech => padtech)
381
           port map (sdcasn, sdo.casn);
382
      sddqm_pad : outpadv generic map (width =>4, tech => padtech)
383
           port map (sddqm, sdo.dqm(3 downto 0));
384
  end generate;
385
  sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
386
           port map (sdcsn, sdo.sdcsn);
387
 
388
  addr_pad : outpadv generic map (width => 28, tech => padtech)
389
        port map (address, memo.address(27 downto 0));
390
  rams_pad : outpadv generic map (width => 5, tech => padtech)
391
        port map (ramsn, memo.ramsn(4 downto 0));
392
  roms_pad : outpadv generic map (width => 2, tech => padtech)
393
        port map (romsn, memo.romsn(1 downto 0));
394
  oen_pad  : outpad generic map (tech => padtech)
395
        port map (oen, memo.oen);
396
  rwen_pad : outpadv generic map (width => 4, tech => padtech)
397
        port map (rwen, memo.wrn);
398
  roen_pad : outpadv generic map (width => 5, tech => padtech)
399
        port map (ramoen, memo.ramoen(4 downto 0));
400
  wri_pad  : outpad generic map (tech => padtech)
401
        port map (writen, memo.writen);
402
  read_pad : outpad generic map (tech => padtech)
403
        port map (read, memo.read);
404
  iosn_pad : outpad generic map (tech => padtech)
405
        port map (iosn, memo.iosn);
406
  bdr : for i in 0 to 3 generate
407
      data_pad : iopadv generic map (tech => padtech, width => 8)
408
      port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
409
        memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
410
  end generate;
411
 
412
----------------------------------------------------------------------
413
---  APB Bridge and various periherals -------------------------------
414
----------------------------------------------------------------------
415
 
416
  apb0 : apbctrl                                -- AHB/APB bridge
417
  generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
418
  port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
419
 
420
  ua1 : if CFG_UART1_ENABLE /= 0 generate
421
    uart1 : apbuart                     -- UART 1
422
    generic map (pindex => 1, paddr => 1,  pirq => 2, console => dbguart,
423
        fifosize => CFG_UART1_FIFO)
424
    port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
425
    u1i.extclk <= '0';
426
    rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
427
    txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
428
    cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
429
    rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
430
  end generate;
431
  noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
432
 
433
  ua2 : if CFG_UART2_ENABLE /= 0 generate
434
    uart2 : apbuart                     -- UART 2
435
    generic map (pindex => 9, paddr => 9,  pirq => 3, fifosize => CFG_UART2_FIFO)
436
    port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
437
    u2i.extclk <= '0';
438
    rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
439
    txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
440
    cts2_pad : inpad generic map (tech => padtech) port map (ctsn2, u2i.ctsn);
441
    rts2_pad : outpad generic map (tech => padtech) port map (rtsn2, u2o.rtsn);
442
  end generate;
443
  noua1 : if CFG_UART2_ENABLE = 0 generate
444
    apbo(9) <= apb_none;  rtsn2 <= '0';
445
  end generate;
446
 
447
  irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
448
    irqctrl0 : irqmp                    -- interrupt controller
449
    generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
450
    port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
451
  end generate;
452
  irq3 : if CFG_IRQ3_ENABLE = 0 generate
453
    x : for i in 0 to CFG_NCPU-1 generate
454
      irqi(i).irl <= "0000";
455
    end generate;
456
    apbo(2) <= apb_none;
457
  end generate;
458
 
459
  gpt : if CFG_GPT_ENABLE /= 0 generate
460
    timer0 : gptimer                    -- timer unit
461
    generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
462
        sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
463
        nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
464
    port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
465
    gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
466
  end generate;
467
  wden : if CFG_GPT_WDOGEN /= 0 generate
468
    wdogl <= gpto.wdogn or not rstn;
469
    wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
470
  end generate;
471
  wddis : if CFG_GPT_WDOGEN = 0 generate
472
    wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc(0));
473
  end generate;
474
 
475
  nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
476
 
477
  kbd : if CFG_KBD_ENABLE /= 0 generate
478
    ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
479
      port map(rstn, clkm, apbi, apbo(4), moui, mouo);
480
    ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
481
      port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
482
  end generate;
483
  nokbd : if CFG_KBD_ENABLE = 0 generate
484
        apbo(4) <= apb_none; mouo <= ps2o_none;
485
        apbo(5) <= apb_none; kbdo <= ps2o_none;
486
  end generate;
487
  kbdclk_pad : iopad generic map (tech => padtech)
488
      port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
489
  kbdata_pad : iopad generic map (tech => padtech)
490
        port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
491
  mouclk_pad : iopad generic map (tech => padtech)
492
      port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
493
  mouata_pad : iopad generic map (tech => padtech)
494
        port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
495
 
496
  vga : if CFG_VGA_ENABLE /= 0 generate
497
    vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
498
       port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
499
    video_clock_pad : outpad generic map ( tech => padtech)
500
        port map (vid_clock, video_clk);
501
    video_clk <= not ethclk;
502
   end generate;
503
 
504
  -- Note: SVGA graphics support removed to make room for SpaceWire Light
505
  assert CFG_SVGA_ENABLE = 0 report "SVGA graphics not supported";
506
  svga : if CFG_SVGA_ENABLE /= 0 generate
507
    ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG) <= ahbm_none;
508
    apbo(6) <= apb_none;
509
    vgao <= vgao_none;
510
    video_clk <= not clkm;
511
    video_clock_pad : outpad generic map ( tech => padtech)
512
        port map (vid_clock, video_clk);
513
  end generate;
514
 
515
  novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
516
    apbo(6) <= apb_none; vgao <= vgao_none;
517
    video_clk <= not clkm;
518
    video_clock_pad : outpad generic map ( tech => padtech)
519
        port map (vid_clock, video_clk);
520
  end generate;
521
 
522
  blank_pad : outpad generic map (tech => padtech)
523
        port map (vid_blankn, vgao.blank);
524
  comp_sync_pad : outpad generic map (tech => padtech)
525
        port map (vid_syncn, vgao.comp_sync);
526
  vert_sync_pad : outpad generic map (tech => padtech)
527
        port map (vid_vsync, vgao.vsync);
528
  horiz_sync_pad : outpad generic map (tech => padtech)
529
        port map (vid_hsync, vgao.hsync);
530
  video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
531
        port map (vid_r, vgao.video_out_r);
532
  video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
533
        port map (vid_g, vgao.video_out_g);
534
  video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
535
        port map (vid_b, vgao.video_out_b);
536
 
537
  gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate     -- GPIO unit
538
    grgpio0: grgpio
539
    generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
540
    port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
541
    gpioi => gpioi, gpioo => gpioo);
542
    p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
543
      pio_pads : for i in 1 to 2 generate
544
        pio_pad : iopad generic map (tech => padtech)
545
            port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
546
      end generate;
547
    end generate;
548
    p1 : if (CFG_CAN = 0) generate
549
      pio_pads : for i in 4 to 5 generate
550
        pio_pad : iopad generic map (tech => padtech)
551
            port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
552
      end generate;
553
    end generate;
554
    pio_pad0 : iopad generic map (tech => padtech)
555
            port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
556
    pio_pad1 : iopad generic map (tech => padtech)
557
            port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
558
    pio_pads : for i in 6 to 17 generate
559
        pio_pad : iopad generic map (tech => padtech)
560
            port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
561
    end generate;
562
 
563
  end generate;
564
 
565
  ahbs : if CFG_AHBSTAT = 1 generate    -- AHB status register
566
    ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
567
        nftslv => CFG_AHBSTATN)
568
      port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
569
  end generate;
570
 
571
-----------------------------------------------------------------------
572
---  ETHERNET ---------------------------------------------------------
573
-----------------------------------------------------------------------
574
 
575
    eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
576
      e1 : grethm generic map(
577
        hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
578
        pindex => 13, paddr => 13, pirq => 13, memtech => memtech,
579
        mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
580
        nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
581
        macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
582
        ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
583
      port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
584
        ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
585
        apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
586
    end generate;
587
 
588
    ethpads : if (CFG_GRETH = 1) generate -- eth pads
589
      emdio_pad : iopad generic map (tech => padtech)
590
      port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
591
      etxc_pad : clkpad generic map (tech => padtech, arch => 2)
592
        port map (etx_clk, ethi.tx_clk);
593
      erxc_pad : clkpad generic map (tech => padtech, arch => 2)
594
        port map (erx_clk, ethi.rx_clk);
595
      erxd_pad : inpadv generic map (tech => padtech, width => 4)
596
        port map (erxd, ethi.rxd(3 downto 0));
597
      erxdv_pad : inpad generic map (tech => padtech)
598
        port map (erx_dv, ethi.rx_dv);
599
      erxer_pad : inpad generic map (tech => padtech)
600
        port map (erx_er, ethi.rx_er);
601
      erxco_pad : inpad generic map (tech => padtech)
602
        port map (erx_col, ethi.rx_col);
603
      erxcr_pad : inpad generic map (tech => padtech)
604
        port map (erx_crs, ethi.rx_crs);
605
      emdint_pad : inpad generic map (tech => padtech)
606
        port map (emdint, ethi.mdint);
607
 
608
      etxd_pad : outpadv generic map (tech => padtech, width => 4)
609
        port map (etxd, etho.txd(3 downto 0));
610
      etxen_pad : outpad generic map (tech => padtech)
611
        port map ( etx_en, etho.tx_en);
612
      etxer_pad : outpad generic map (tech => padtech)
613
        port map (etx_er, etho.tx_er);
614
      emdc_pad : outpad generic map (tech => padtech)
615
        port map (emdc, etho.mdc);
616
    end generate;
617
 
618
-----------------------------------------------------------------------
619
---  AHB RAM ----------------------------------------------------------
620
-----------------------------------------------------------------------
621
 
622
  ocram : if CFG_AHBRAMEN = 1 generate
623
    ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
624
        tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
625
    port map ( rstn, clkm, ahbsi, ahbso(7));
626
  end generate;
627
 
628
-----------------------------------------------------------------------
629
---  Multi-core CAN ---------------------------------------------------
630
-----------------------------------------------------------------------
631
 
632
   can0 : if CFG_CAN = 1 generate
633
     can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
634
        iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
635
        ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
636
      port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
637
      can_tx_pad1 : iopad generic map (tech => padtech)
638
            port map (pio(5), can_ltx(0), gnd(0), gpioi.din(5));
639
      can_rx_pad1 : iopad generic map (tech => padtech)
640
            port map (pio(4), gnd(0), vcc(0), can_lrx(0));
641
      canpas : if CFG_CAN_NUM = 2 generate
642
        can_tx_pad2 : iopad generic map (tech => padtech)
643
            port map (pio(2), can_ltx(1), gnd(0), gpioi.din(2));
644
        can_rx_pad2 : iopad generic map (tech => padtech)
645
            port map (pio(1), gnd(0), vcc(0), can_lrx(1));
646
      end generate;
647
   end generate;
648
 
649
   -- standby controlled by pio(3) and pio(0)
650
 
651
-----------------------------------------------------------------------
652
---  SpaceWire Light --------------------------------------------------
653
-----------------------------------------------------------------------
654
 
655
   spw0: spwamba
656
      generic map (
657
         tech        => memtech,
658
         hindex      => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
659
         pindex      => 10,
660
         paddr       => 10,
661
         pirq        => 10,
662
         sysfreq     => real(CPU_FREQ) * 1000.0,
663
         txclkfreq   => 200.0e6,
664
         rximpl      => impl_fast,
665
         rxchunk     => 4,
666
         tximpl      => impl_fast,
667
         timecodegen => true,
668
         rxfifosize  => 8,
669
         txfifosize  => 8,
670
         desctablesize => 10,
671
         maxburst    => 3 )
672
      port map (
673
         clk     => clkm,
674
         rxclk   => spw_clkl,
675
         txclk   => spw_clkl,
676
         rstn    => rstn,
677
         apbi    => apbi,
678
         apbo    => apbo(10),
679
         ahbi    => ahbmi,
680
         ahbo    => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
681
         tick_in => spw_tick_in,
682
         spw_di  => spw_di,
683
         spw_si  => spw_si,
684
         spw_do  => spw_do,
685
         spw_so  => spw_so );
686
 
687
   spw_rxd_pad: inpad_ds
688
      generic map (padtech, lvds, x25v)
689
      port map (spw_rxdp(0), spw_rxdn(0), spw_di);
690
   spw_rxs_pad: inpad_ds
691
      generic map (padtech, lvds, x25v)
692
      port map (spw_rxsp(0), spw_rxsn(0), spw_si);
693
   spw_txd_pad: outpad_ds
694
      generic map (padtech, lvds, x25v)
695
      port map (spw_txdp(0), spw_txdn(0), spw_do, '0');
696
   spw_txs_pad: outpad_ds
697
      generic map (padtech, lvds, x25v)
698
      port map (spw_txsp(0), spw_txsn(0), spw_so, '0');
699
 
700
   -- Use 2nd GPTIMER unit to generate external tick_in signal.
701
   spw_tick_in <= gpto.tick(2) when CFG_GPT_ENABLE /= 0 else '0';
702
 
703
   -- Generate 200 MHz clock for fast receiver/transmitter.
704
   spwclk0: DCM
705
      generic map (
706
         CLKFX_DIVIDE       => 1,
707
         CLKFX_MULTIPLY     => 4,
708
         CLK_FEEDBACK       => "NONE",
709
         CLKIN_DIVIDE_BY_2  => false,
710
         CLKIN_PERIOD       => 20.0,
711
         CLKOUT_PHASE_SHIFT => "NONE",
712
         DESKEW_ADJUST      => "SYSTEM_SYNCHRONOUS",
713
         DFS_FREQUENCY_MODE => "LOW",
714
         DUTY_CYCLE_CORRECTION => true,
715
         STARTUP_WAIT       => false )
716
      port map (
717
         CLKIN      => lclk,
718
         RST        => not rstraw,
719
         CLKFX      => spw_clkl );
720
 
721
-------------------------------------------------------------------------------
722
--- USB -----------------------------------------------------------------------
723
-------------------------------------------------------------------------------
724
  -- Note that the GRUSBDC and GRUSB_DCL can not be instantiated at the same
725
  -- time (board has only one USB transceiver), therefore they share AHB
726
  -- master/slave indexes
727
  -----------------------------------------------------------------------------
728
  -- Shared pads
729
  -----------------------------------------------------------------------------
730
  usbpads: if (CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
731
    usb_clk_pad : clkpad generic map (tech => padtech, arch => 2)
732
      port map (usb_clkout, uclk);
733
 
734
    usb_d_pad: iopadv generic map(tech => padtech, width => 16, slew => 1)
735
      port map (usb_d, usbo.dataout, usbo.oen, usbi.datain);
736
 
737
    usb_txready_pad : inpad generic map (tech => padtech)
738
      port map (usb_txready,usbi.txready);
739
    usb_rxvalid_pad : inpad generic map (tech => padtech)
740
      port map (usb_rxvalid,usbi.rxvalid);
741
    usb_rxerror_pad : inpad generic map (tech => padtech)
742
      port map (usb_rxerror,usbi.rxerror);
743
    usb_rxactive_pad : inpad generic map (tech => padtech)
744
      port map (usb_rxactive,usbi.rxactive);
745
    usb_linestate_pad : inpadv generic map (tech => padtech, width => 2)
746
      port map (usb_linestate,usbi.linestate);
747
    usb_vbus_pad : inpad generic map (tech => padtech)
748
      port map (usb_vbus, usbi.vbusvalid);
749
 
750
    usb_reset_pad : outpad generic map (tech => padtech, slew => 1)
751
      port map (usb_reset,usbo.reset);
752
    usb_suspend_pad : outpad generic map (tech => padtech, slew => 1)
753
      port map (usb_suspend,usbo.suspendm);
754
    usb_termsel_pad : outpad generic map (tech => padtech, slew => 1)
755
      port map (usb_termsel,usbo.termselect);
756
    usb_xcvrsel_pad : outpad generic map (tech => padtech, slew => 1)
757
      port map (usb_xcvrsel,usbo.xcvrselect(0));
758
    usb_txvalid_pad : outpad generic map (tech => padtech, slew => 1)
759
      port map (usb_txvalid,usbo.txvalid);
760
    usb_opmode_pad : outpadv generic map (tech =>padtech ,width =>2, slew =>1)
761
      port map (usb_opmode,usbo.opmode);
762
 
763
    usb_validh_pad:iopad generic map(tech => padtech, slew => 1)
764
      port map (usb_validh, usbo.txvalidh, usbo.oen, usbi.rxvalidh);
765
 
766
  end generate;
767
 
768
  -----------------------------------------------------------------------------
769
  -- USB 2.0 Device Controller
770
  -----------------------------------------------------------------------------
771
  usbdc0: if CFG_GRUSBDC = 1 generate
772
    usbdc0: grusbdc
773
      generic map(
774
        hsindex => 5, hirq => 9, haddr => 16#004#, hmask => 16#FFC#,
775
        hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
776
        CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
777
        aiface => CFG_GRUSBDC_AIFACE, uiface => 0, dwidth => CFG_GRUSBDC_DW,
778
        nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
779
        i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
780
        i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
781
        i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
782
        i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
783
        i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
784
        i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
785
        i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
786
        i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
787
        o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
788
        o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
789
        o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
790
        o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
791
        o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
792
        o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
793
        o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
794
        o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
795
        memtech => memtech)
796
      port map(
797
        uclk  => uclk,
798
        usbi  => usbi,
799
        usbo  => usbo,
800
        hclk  => clkm,
801
        hrst  => rstn,
802
        ahbmi => ahbmi,
803
        ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
804
                       CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN),
805
        ahbsi => ahbsi,
806
        ahbso => ahbso(5)
807
        );
808
  end generate usbdc0;
809
 
810
  -----------------------------------------------------------------------------
811
  -- USB DCL
812
  -----------------------------------------------------------------------------
813
  usb_dcl0: if CFG_GRUSB_DCL = 1 generate
814
    usb_dcl0: grusb_dcl
815
      generic map (
816
        hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
817
        CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
818
        memtech => memtech, uiface => 0, dwidth => CFG_GRUSB_DCL_DW)
819
      port map (
820
        uclk, usbi, usbo, clkm, rstn, ahbmi,
821
        ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
822
              CFG_SPW_NUM*CFG_SPW_EN));
823
  end generate usb_dcl0;
824
 
825
-----------------------------------------------------------------------
826
---  AHB ATA ----------------------------------------------------------
827
-----------------------------------------------------------------------
828
 
829
  ata0 : if CFG_ATA = 1 generate
830
    atac0 : atactrl
831
      generic map(
832
        tech => 0, fdepth => CFG_ATAFIFO,
833
        mhindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
834
        CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
835
        CFG_GRUSBDC,
836
        shindex => 3, haddr => 16#A00#, hmask => 16#fff#, pirq  => CFG_ATAIRQ,
837
        mwdma => CFG_ATADMA, TWIDTH   => 8,
838
        -- PIO mode 0 settings (@100MHz clock)
839
        PIO_mode0_T1   => 6,   -- 70ns
840
        PIO_mode0_T2   => 28,  -- 290ns
841
        PIO_mode0_T4   => 2,   -- 30ns
842
        PIO_mode0_Teoc => 23   -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
843
        )
844
      port map(
845
        rst => rstn, arst => vcc(0), clk => clkm, ahbmi => ahbmi,
846
        ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
847
                       CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+
848
                       CFG_GRUSB_DCL+CFG_GRUSBDC),
849
        ahbsi => ahbsi, ahbso => ahbso(3), atai => idei, atao => ideo);
850
 
851
    ata_rstn_pad : outpad generic map (tech => padtech)
852
      port map (ata_rstn, ideo.rstn);
853
    ata_data_pad : iopadv generic map (tech => padtech, width => 16, oepol => 1)
854
      port map (ata_data, ideo.ddo, ideo.oen, idei.ddi);
855
    ata_da_pad : outpadv generic map (tech => padtech, width => 3)
856
      port map (ata_da, ideo.da);
857
    ata_cs0_pad : outpad generic map (tech => padtech)
858
      port map (ata_cs0, ideo.cs0);
859
    ata_cs1_pad : outpad generic map (tech => padtech)
860
      port map (ata_cs1, ideo.cs1);
861
    ata_dior_pad : outpad generic map (tech => padtech)
862
      port map (ata_dior, ideo.dior);
863
    ata_diow_pad : outpad generic map (tech => padtech)
864
      port map (ata_diow, ideo.diow);
865
    iordy_pad : inpad generic map (tech => padtech)
866
      port map (ata_iordy, idei.iordy);
867
    intrq_pad : inpad generic map (tech => padtech)
868
      port map (ata_intrq, idei.intrq);
869
    dmarq_pad : inpad generic map (tech => padtech)
870
      port map (ata_dmarq, idei.dmarq);
871
    dmack_pad : outpad generic map (tech => padtech)
872
      port map (ata_dmack, ideo.dmack);
873
    ata_csel <= '0';
874
  end generate;
875
 
876
-----------------------------------------------------------------------
877
---  Drive unused bus elements  ---------------------------------------
878
-----------------------------------------------------------------------
879
 
880
--  nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
881
--    ahbmo(i) <= ahbm_none;
882
--  end generate;
883
--  nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
884
--  nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
885
 
886
-----------------------------------------------------------------------
887
---  Boot message  ----------------------------------------------------
888
-----------------------------------------------------------------------
889
 
890
-- pragma translate_off
891
  x : report_version
892
  generic map (
893
   msg1 => "LEON3 GR-XC3S-1500 Demonstration design",
894
      msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
895
        & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
896
   msg3 => "Target technology: " & tech_table(fabtech) & ",  memory library: " & tech_table(memtech),
897
   mdel => 1
898
  );
899
-- pragma translate_on
900
end;

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