OpenCores
URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [syn/] [spwstream_gr-xc3s1500/] [spwstream_top.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jorisvr
library ieee;
2
use ieee.std_logic_1164.all, ieee.numeric_std.all;
3
use work.spwpkg.all;
4
 
5
entity spwstream_top is
6
 
7
    port (
8
        clk:        in  std_logic;
9
        fastclk:    in  std_logic;
10
        rst:        in  std_logic;
11
        autostart:  in  std_logic;
12
        linkstart:  in  std_logic;
13
        linkdis:    in  std_logic;
14
        txdivcnt:   in  std_logic_vector(7 downto 0);
15
        tick_in:    in  std_logic;
16
        ctrl_in:    in  std_logic_vector(1 downto 0);
17
        time_in:    in  std_logic_vector(5 downto 0);
18
        txwrite:    in  std_logic;
19
        txflag:     in  std_logic;
20
        txdata:     in  std_logic_vector(7 downto 0);
21
        txrdy:      out std_logic;
22
        txhalff:    out std_logic;
23
        tick_out:   out std_logic;
24
        ctrl_out:   out std_logic_vector(1 downto 0);
25
        time_out:   out std_logic_vector(5 downto 0);
26
        rxvalid:    out std_logic;
27
        rxhalff:    out std_logic;
28
        rxflag:     out std_logic;
29
        rxdata:     out std_logic_vector(7 downto 0);
30
        rxread:     in  std_logic;
31
        started:    out std_logic;
32
        connecting: out std_logic;
33
        running:    out std_logic;
34
        errdisc:    out std_logic;
35
        errpar:     out std_logic;
36
        erresc:     out std_logic;
37
        errcred:    out std_logic;
38
        spw_di:     in  std_logic;
39
        spw_si:     in  std_logic;
40
        spw_do:     out std_logic;
41
        spw_so:     out std_logic
42
    );
43
 
44
end entity spwstream_top;
45
 
46
architecture spwstream_top_arch of spwstream_top is
47
 
48
begin
49
 
50
    spwstream_inst: spwstream
51
        generic map (
52
            sysfreq         => 60.0e6,
53 3 jorisvr
            txclkfreq       => 240.0e6,
54 2 jorisvr
            rximpl          => impl_fast,
55
            rxchunk         => 4,
56
            tximpl          => impl_fast,
57
            rxfifosize_bits => 11,
58
            txfifosize_bits => 6 )
59
        port map (
60
            clk         => clk,
61
            rxclk       => fastclk,
62
            txclk       => fastclk,
63
            rst         => rst,
64
            autostart   => autostart,
65
            linkstart   => linkstart,
66
            linkdis     => linkdis,
67
            txdivcnt    => txdivcnt,
68
            tick_in     => tick_in,
69
            ctrl_in     => ctrl_in,
70
            time_in     => time_in,
71
            txwrite     => txwrite,
72
            txflag      => txflag,
73
            txdata      => txdata,
74
            txrdy       => txrdy
75
,           txhalff     => txhalff,
76
            tick_out    => tick_out,
77
            ctrl_out    => ctrl_out,
78
            time_out    => time_out,
79
            rxvalid     => rxvalid,
80
            rxhalff     => rxhalff,
81
            rxflag      => rxflag,
82
            rxdata      => rxdata,
83
            rxread      => rxread,
84
            started     => started,
85
            connecting  => connecting,
86
            running     => running,
87
            errdisc     => errdisc,
88
            errpar      => errpar,
89
            erresc      => erresc,
90
            errcred     => errcred,
91
            spw_di      => spw_di,
92
            spw_si      => spw_si,
93
            spw_do      => spw_do,
94
            spw_so      => spw_so );
95
 
96
end architecture spwstream_top_arch;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.