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[/] [spacewire_light/] [trunk/] [syn/] [streamtest_digilent-xc3s200/] [streamtest_top.vhd] - Blame information for rev 3

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Line No. Rev Author Line
1 2 jorisvr
--
2
--  Test of spwstream on Digilent XC3S200 board.
3 3 jorisvr
--  60 MHz system clock, 200 MHz receive clock and transmit clock.
4 2 jorisvr
--
5
--  LED 0 = link started
6
--  LED 1 = link connecting
7
--  LED 2 = link run
8
--  LED 3 = link error (sticky until clear button)
9
--  LED 4 = gotdata
10
--  LED 5 = off
11
--  LED 6 = data error (sticky until reset)
12
--  LED 7 = time code error (sticky until reset)
13
--
14
--  Button 0 = reset
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--  Button 1 = clear LED 3
16
--
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--  Switch 0 = link autostart
18
--  Switch 1 = link start
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--  Switch 2 = link disable
20
--  Switch 3 = send data and time codes
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--  Switch 4-7 = bits 0-3 of tx bit rate scale factor
22
--
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--  SpaceWire signals on A2 expansion connector:
24
--    Data In    pos,neg  =  B5,C5  =  pin 19,6
25
--    Strobe In  pos,neg  =  D6,E6  =  pin 7,4
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--    Data Out   pos,neg  =  B6,C6  =  pin 21,8
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--    Strobe Out pos,neg  =  D7,E7  =  pin 11,9
28
--
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--  Note: these are not true LVDS signals; they are configured as LVDS25
30
--  but powered from 3.3V instead of 2.5V, not differentially routed and
31
--  not properly terminated.
32
--
33
--  The SpaceWire port should be looped back to itself with wires from
34
--  outputs to corresponding inputs.
35
--
36
 
37
library ieee;
38
use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library unisim;
40
use unisim.vcomponents.all;
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use work.spwpkg.all;
42
 
43
entity streamtest_top is
44
 
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    port (
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        clk50:      in  std_logic;
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        button:     in  std_logic_vector(3 downto 0);
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        switch:     in  std_logic_vector(7 downto 0);
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        led:        out std_logic_vector(7 downto 0);
50
        spw_di_p:   in  std_logic;
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        spw_di_n:   in  std_logic;
52
        spw_si_p:   in  std_logic;
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        spw_si_n:   in  std_logic;
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        spw_do_p:   out std_logic;
55
        spw_do_n:   out std_logic;
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        spw_so_p:   out std_logic;
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        spw_so_n:   out std_logic );
58
 
59
end entity streamtest_top;
60
 
61
architecture streamtest_top_arch of streamtest_top is
62
 
63
    -- Clock generation.
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    signal boardclk:        std_logic;
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    signal sysclk:          std_logic;
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    signal fastclk:         std_logic;
67
 
68
    -- Synchronize buttons
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    signal s_resetbtn:      std_logic := '0';
70
    signal s_clearbtn:      std_logic := '0';
71
 
72
    -- Sticky LED
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    signal s_linkerrorled:  std_logic := '0';
74
 
75
    -- Interface signals.
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    signal s_rst:           std_logic := '1';
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    signal s_linkstart:     std_logic := '0';
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    signal s_autostart:     std_logic := '0';
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    signal s_linkdisable:   std_logic := '0';
80
    signal s_senddata:      std_logic := '0';
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    signal s_txdivcnt:      std_logic_vector(7 downto 0) := "00000000";
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    signal s_linkstarted:   std_logic;
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    signal s_linkconnecting: std_logic;
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    signal s_linkrun:       std_logic;
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    signal s_linkerror:     std_logic;
86
    signal s_gotdata:       std_logic;
87
    signal s_dataerror:     std_logic;
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    signal s_tickerror:     std_logic;
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    signal s_spwdi:         std_logic;
90
    signal s_spwsi:         std_logic;
91
    signal s_spwdo:         std_logic;
92
    signal s_spwso:         std_logic;
93
 
94
    -- Make clock nets visible to UCF file.
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    attribute KEEP: string;
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    attribute KEEP of sysclk: signal is "SOFT";
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    attribute KEEP of fastclk: signal is "SOFT";
98
 
99
    component streamtest is
100
        generic (
101
            sysfreq:    real;
102 3 jorisvr
            txclkfreq:  real;
103 2 jorisvr
            tickdiv:    integer range 12 to 24 := 20;
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            rximpl:     spw_implementation_type := impl_generic;
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            rxchunk:    integer range 1 to 4 := 1;
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            tximpl:     spw_implementation_type := impl_generic;
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            rxfifosize_bits: integer range 6 to 14 := 11;
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            txfifosize_bits: integer range 2 to 14 := 11 );
109
        port (
110
            clk:        in  std_logic;
111
            rxclk:      in  std_logic;
112
            txclk:      in  std_logic;
113
            rst:        in  std_logic;
114
            linkstart:  in  std_logic;
115
            autostart:  in  std_logic;
116
            linkdisable: in std_logic;
117
            senddata:   in  std_logic;
118
            sendtick:   in  std_logic;
119
            txdivcnt:   in  std_logic_vector(7 downto 0);
120
            linkstarted: out std_logic;
121
            linkconnecting: out std_logic;
122
            linkrun:    out std_logic;
123
            linkerror:  out std_logic;
124
            gotdata:    out std_logic;
125
            dataerror:  out std_logic;
126
            tickerror:  out std_logic;
127
            spw_di:     in  std_logic;
128
            spw_si:     in  std_logic;
129
            spw_do:     out std_logic;
130
            spw_so:     out std_logic );
131
    end component;
132
 
133
begin
134
 
135
    -- Buffer incoming clock.
136
    bufg0: BUFG port map ( I => clk50, O => boardclk );
137
 
138
    -- Generate 60 MHz system clock.
139
    dcm0: DCM
140
        generic map (
141
            CLKFX_DIVIDE        => 5,
142
            CLKFX_MULTIPLY      => 6,
143
            CLK_FEEDBACK      => "NONE",
144
            CLKIN_DIVIDE_BY_2   => false,
145
            CLKIN_PERIOD        => 20.0,
146
            CLKOUT_PHASE_SHIFT  => "NONE",
147
            DESKEW_ADJUST       => "SYSTEM_SYNCHRONOUS",
148
            DFS_FREQUENCY_MODE  => "LOW",
149
            DUTY_CYCLE_CORRECTION => true,
150
            STARTUP_WAIT        => true )
151
        port map (
152
            CLKIN       => boardclk,
153
            RST         => '0',
154
            CLKFX       => sysclk );
155
 
156
    -- Generate 200 MHz fast clock.
157
    dcm1: DCM
158
        generic map (
159
            CLKFX_DIVIDE        => 1,
160
            CLKFX_MULTIPLY      => 4,
161
            CLK_FEEDBACK        => "NONE",
162
            CLKIN_DIVIDE_BY_2   => false,
163
            CLKIN_PERIOD        => 20.0,
164
            CLKOUT_PHASE_SHIFT  => "NONE",
165
            DESKEW_ADJUST       => "SYSTEM_SYNCHRONOUS",
166
            DFS_FREQUENCY_MODE  => "LOW",
167
            DUTY_CYCLE_CORRECTION => true,
168
            STARTUP_WAIT        => true )
169
        port map (
170
            CLKIN       => boardclk,
171
            RST         => '0',
172
            CLKFX       => fastclk );
173
 
174
    -- Streamtest instance
175
    streamtest_inst: streamtest
176
        generic map (
177
            sysfreq     => 60.0e6,
178 3 jorisvr
            txclkfreq   => 200.0e6,
179 2 jorisvr
            tickdiv     => 22,
180
            rximpl      => impl_fast,
181
            rxchunk     => 4,
182
            tximpl      => impl_fast,
183
            rxfifosize_bits => 11,
184
            txfifosize_bits => 10 )
185
        port map (
186
            clk         => sysclk,
187
            rxclk       => fastclk,
188
            txclk       => fastclk,
189
            rst         => s_rst,
190
            linkstart   => s_linkstart,
191
            autostart   => s_autostart,
192
            linkdisable => s_linkdisable,
193
            senddata    => s_senddata,
194
            sendtick    => s_senddata,
195
            txdivcnt    => s_txdivcnt,
196
            linkstarted => s_linkstarted,
197
            linkconnecting => s_linkconnecting,
198
            linkrun     => s_linkrun,
199
            linkerror   => s_linkerror,
200
            gotdata     => s_gotdata,
201
            dataerror   => s_dataerror,
202
            tickerror   => s_tickerror,
203
            spw_di      => s_spwdi,
204
            spw_si      => s_spwsi,
205
            spw_do      => s_spwdo,
206
            spw_so      => s_spwso );
207
 
208
    -- LVDS buffers
209
    spwdi_pad: IBUFDS
210
        generic map ( IOSTANDARD => "LVDS_25" )
211
        port map ( O => s_spwdi, I => spw_di_p, IB => spw_di_n );
212
    spwsi_pad: IBUFDS
213
        generic map ( IOSTANDARD => "LVDS_25" )
214
        port map ( O => s_spwsi, I => spw_si_p, IB => spw_si_n );
215
    spwdo_pad: OBUFDS
216
        generic map ( IOSTANDARD => "LVDS_25" )
217
        port map ( O => spw_do_p, OB => spw_do_n, I => s_spwdo );
218
    spwso_pad: OBUFDS
219
        generic map ( IOSTANDARD => "LVDS_25" )
220
        port map ( O => spw_so_p, OB => spw_so_n, I => s_spwso );
221
 
222
    process (sysclk) is
223
    begin
224
        if rising_edge(sysclk) then
225
 
226
            -- Synchronize buttons
227
            s_resetbtn  <= button(0);
228
            s_rst       <= s_resetbtn;
229
            s_clearbtn  <= button(1);
230
 
231
            -- Synchronize switch settings
232
            s_autostart <= switch(0);
233
            s_linkstart <= switch(1);
234
            s_linkdisable <= switch(2);
235
            s_senddata  <= switch(3);
236
            s_txdivcnt(3 downto 0) <= switch(7 downto 4);
237
 
238
            -- Sticky link error LED
239
            s_linkerrorled <= (s_linkerrorled or s_linkerror) and
240
                              (not s_clearbtn) and
241
                              (not s_resetbtn);
242
 
243
            -- Drive LEDs
244
            led(0)  <= s_linkstarted;
245
            led(1)  <= s_linkconnecting;
246
            led(2)  <= s_linkrun;
247
            led(3)  <= s_linkerrorled;
248
            led(4)  <= s_gotdata;
249
            led(5)  <= '0';
250
            led(6)  <= s_dataerror;
251
            led(7)  <= s_tickerror;
252
 
253
        end if;
254
    end process;
255
 
256
end architecture streamtest_top_arch;

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