OpenCores
URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [syn/] [streamtest_gr-xc3s1500/] [Makefile] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 jorisvr
 
2
###############################################################################
3
##                                                                           ##
4
##                        project-dependent variables                        ##
5
##                                                                           ##
6
###############################################################################
7
 
8
# The project name. The bit-file that is generated in the end will be named
9
# "$(PROJ).bit"
10
 
11
PROJ = streamtest
12
 
13
# The top-level entity to be instantiated
14
 
15
TOPLEVEL = streamtest_top
16
 
17
# The VHDL sources that need to be compiled during synthesis
18
 
19
RTLDIR = ../../rtl/vhdl
20
VHDL_SOURCES = streamtest_top.vhd \
21
               $(RTLDIR)/streamtest.vhd \
22
               $(RTLDIR)/spwpkg.vhd \
23
               $(RTLDIR)/spwstream.vhd \
24
               $(RTLDIR)/spwlink.vhd \
25
               $(RTLDIR)/spwram.vhd \
26
               $(RTLDIR)/spwrecv.vhd \
27
               $(RTLDIR)/spwxmit.vhd \
28
               $(RTLDIR)/spwxmit_fast.vhd \
29
               $(RTLDIR)/spwrecvfront_generic.vhd \
30
               $(RTLDIR)/spwrecvfront_fast.vhd
31
 
32
# For Pender XC3S1500 board
33
FPGA_TYPE       = xc3s1500-fg456-4
34
 
35
## For Pender XC3S2000 rev2 board
36
#FPGA_TYPE      = xc3s2000-fg456-4
37
 
38
# The default target; recommended targets: "bitfile" or "upload"
39
 
40
default : bitfile
41
 
42
UCFFILE = streamtest.ucf
43
 
44
###############################################################################
45
##                                                                           ##
46
##            miscellaneous project-independent variables & rules            ##
47
##                                                                           ##
48
###############################################################################
49
 
50
# use this to make most tools quieter
51
OPT_INTSTYLE = -intstyle ise
52
 
53
# Phony (non file creating) targets
54
 
55
.PHONY : default clean bitfile
56
 
57
clean :
58
        $(RM) -rf *~ work dump.xst _ngo 'file graph' xlnx_auto_0_xdb
59
        $(RM) $(PROJ).xst-script
60
        $(RM) $(PROJ).lso $(PROJ).prj
61
        $(RM) $(PROJ).ngc $(PROJ).xst.log $(PROJ).syr $(PROJ).srp $(PROJ).ngr
62
        $(RM) $(PROJ).ngd $(PROJ).bld
63
        $(RM) $(PROJ).twx $(PROJ).twr
64
        $(RM) $(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm
65
        $(RM) $(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt
66
        $(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drc
67
        $(RM) $(PROJ).ptwx $(PROJ).unroutes *.xrpt $(PROJ)_summary.xml $(PROJ)_usage.xml $(PROJ)_map.map
68
 
69
bitfile : $(PROJ).bit
70
 
71
###############################################################################
72
#                                                                             #
73
#                    STAGE 1: "xst" (Xilinx Synthesis Tool)                   #
74
#  needs:                                                                     #
75
#                                                                             #
76
#    $(PROJ).vhdl                                                             #
77
#    $(PROJ).prj - Project file (created below)                               #
78
#    $(PROJ).lso - Library Search Order file (created below)                  #
79
#                                                                             #
80
#  created files:                                                             #
81
#                                                                             #
82
#    $(PROJ).ngc     - netlist                                                #
83
#    $(PROJ).ngr     - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e       #
84
#                      (optional, depending on the '-rtlview' option)         #
85
#    $(PROJ).xst.log - human-readable synthesis report                        #
86
#                      (AKA .syr, .srp)                                       #
87
#                                                                             #
88
#  created directories:                                                       #
89
#                                                                             #
90
#    work                                                                     #
91
#    dump.xst                                                                 #
92
#                                                                             #
93
###############################################################################
94
 
95
# Generate a "Library Search Order" file, containing just "work" for now.
96
 
97
$(PROJ).lso :
98
        @echo "work" > $@
99
 
100
# Generate a "Project" file, consisting of lines containing each of the
101
# VHDL_SOURCES, preceded by "vhdl work".
102
 
103
$(PROJ).prj :
104
        $(shell echo -n $(VHDL_SOURCES) | \
105
        sed 's/\([^ ]\+\) */vhdl work \1\n/g' > $@)
106
 
107
$(PROJ).xst-script :
108
        @echo "set -tmpdir /tmp"                                        > $@
109
        @echo "set -xsthdpdir ."                                       >> $@
110
        @echo "run"                                                    >> $@
111
        @echo "-ifn                                  $(PROJ).prj"      >> $@
112
        @echo "-ifmt                                 mixed"            >> $@
113
        @echo "-ofn                                  $(PROJ)"          >> $@
114
        @echo "-ofmt                                 ngc"              >> $@
115
        @echo "-p                                    $(FPGA_TYPE)"     >> $@
116
        @echo "-top                                  $(TOPLEVEL)"      >> $@
117
        @echo "-opt_mode                             speed"            >> $@
118
        @echo "-opt_level                            1"                >> $@
119
        @echo "-iuc                                  no"               >> $@
120
        @echo "-lso                                  $(PROJ).lso"      >> $@
121
        @echo "-keep_hierarchy                       no"               >> $@
122
        @echo "-glob_opt                             AllClockNets"     >> $@
123
        @echo "-rtlview                              no"               >> $@
124
        @echo "-read_cores                           yes"              >> $@
125
# Note: write_timing_constraints is non-standard
126
        @echo "-write_timing_constraints             yes"              >> $@
127
        @echo "-cross_clock_analysis                 no"               >> $@
128
#       @echo "-hierarchy_separator                  _"                >> $@
129
        @echo "-bus_delimiter                        <>"               >> $@
130
        @echo "-case                                 maintain"         >> $@
131
        @echo "-slice_utilization_ratio              100"              >> $@
132
#       @echo "-verilog2001                          yes"              >> $@
133
#       @echo "-vlgincdir"                                             >> $@
134
        @echo "-fsm_extract                          yes"              >> $@
135
        @echo "-fsm_encoding                         auto"             >> $@
136
        @echo "-fsm_style                            lut"              >> $@
137
# Note: safe_implementation is non-standard
138
        @echo "-safe_implementation                  yes"              >> $@
139
        @echo "-ram_extract                          yes"              >> $@
140
        @echo "-ram_style                            auto"             >> $@
141
        @echo "-rom_extract                          yes"              >> $@
142
        @echo "-rom_style                            auto"             >> $@
143
        @echo "-mux_extract                          yes"              >> $@
144
        @echo "-mux_style                            auto"             >> $@
145
        @echo "-decoder_extract                      yes"              >> $@
146
        @echo "-priority_extract                     yes"              >> $@
147
        @echo "-shreg_extract                        yes"              >> $@
148
        @echo "-shift_extract                        yes"              >> $@
149
        @echo "-xor_collapse                         yes"              >> $@
150
        @echo "-resource_sharing                     yes"              >> $@
151
        @echo "-mult_style                           auto"             >> $@
152
        @echo "-iobuf                                yes"              >> $@
153
        @echo "-max_fanout                           500"              >> $@
154
        @echo "-bufg                                 8"                >> $@
155
        @echo "-register_duplication                 yes"              >> $@
156
        @echo "-equivalent_register_removal          yes"              >> $@
157
        @echo "-register_balancing                   no"               >> $@
158
        @echo "-slice_packing                        yes"              >> $@
159
        @echo "-optimize_primitives                  no"               >> $@
160
        @echo "-iob                                  auto"             >> $@
161
 
162
$(PROJ).ngc $(PROJ).xst.log : $(VHDL_SOURCES) $(PROJ).prj $(PROJ).lso $(PROJ).xst-script
163
        rm -rf work dump.xst
164
        xst $(OPT_INTSTYLE) -ifn $(PROJ).xst-script -ofn $(PROJ).xst.log
165
        rm -rf work dump.xst
166
 
167
###############################################################################
168
#                                                                             #
169
#                               STAGE 2: ngdbuild                             #
170
#  needs:                                                                     #
171
#                                                                             #
172
#    $(PROJ).ngc                                                              #
173
#                                                                             #
174
#  created files:                                                             #
175
#                                                                             #
176
#    $(PROJ).bld - human-readable build log                                   #
177
#    $(PROJ).ngd - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e           #
178
#                                                                             #
179
#  created dir:                                                               #
180
#    _ngo                                                                     #
181
#                                                                             #
182
###############################################################################
183
 
184
$(PROJ).ngd $(PROJ).bld: $(PROJ).ngc $(UCFFILE)
185
        rm -rf _ngo
186
        ngdbuild $(OPT_INTSTYLE) -dd _ngo -aul -p $(FPGA_TYPE) $(if $(UCFFILE),-uc $(UCFFILE)) $(PROJ).ngc $(PROJ).ngd
187
        rm -rf _ngo
188
 
189
###############################################################################
190
#                                                                             #
191
#                                STAGE 3: Mapper                              #
192
#  needs:                                                                     #
193
#                                                                             #
194
#    $(PROJ).ngd                                                              #
195
#                                                                             #
196
#  created files:                                                             #
197
#                                                                             #
198
#    $(PROJ).pcf     - ASCII file                                             #
199
#    $(PROJ)_map.mrp - human-readable mapping report                          #
200
#    $(PROJ)_map.ncd - binary format                                          #
201
#    $(PROJ)_map.ngm - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e       #
202
#                                                                             #
203
#  NOTE:                                                                      #
204
#                                                                             #
205
#    In order to prevent the make process from terminating on these spurious  #
206
#    problems, we precede the "map" invocation with a hyphen, instructing     #
207
#    make to ignore the return code from "map".                               #
208
#                                                                             #
209
###############################################################################
210
 
211
$(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm: $(PROJ).ngd
212
        map $(OPT_INTSTYLE) -p $(FPGA_TYPE) -cm area -pr b -c 100 -o $(PROJ)_map.ncd $(PROJ).ngd $(PROJ).pcf
213
 
214
###############################################################################
215
#                                                                             #
216
#                          STAGE 4: Place-and-Route                           #
217
#  needs:                                                                     #
218
#                                                                             #
219
#    $(PROJ).pcf                                                              #
220
#    $(PROJ)_map.ncd                                                          #
221
#                                                                             #
222
#  created files:                                                             #
223
#                                                                             #
224
#    $(PROJ).ncd     - binary file                                            #
225
#    $(PROJ).pad     - ASCII file for import in spreadsheet                   #
226
#    $(PROJ).par     - human-readable place-and-route report                  #
227
#    $(PROJ).xpi     - ASCII file                                             #
228
#    $(PROJ)_pad.csv - human-readable CVS file                                #
229
#    $(PROJ)_pad.txt - human-readable file                                    #
230
#                                                                             #
231
###############################################################################
232
 
233
$(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt: $(PROJ).pcf $(PROJ)_map.ncd
234
        par -w $(OPT_INTSTYLE) -t 1 $(PROJ)_map.ncd $(PROJ).ncd $(PROJ).pcf
235
 
236
###############################################################################
237
#                                                                             #
238
#                         STAGE 4.5 (optional): trace                         #
239
#  needs:                                                                     #
240
#                                                                             #
241
#  created files:                                                             #
242
#                                                                             #
243
###############################################################################
244
 
245
$(PROJ).twr $(PROJ).twx : $(PROJ).ncd $(PROJ).pcf
246
        trce $(OPT_INTSTYLE) -e 5 -l 5 -u 5 -xml $(PROJ) $(PROJ).ncd -o $(PROJ).twr $(PROJ).pcf
247
 
248
###############################################################################
249
#                                                                             #
250
#                          STAGE 5: Generate BIT-file                         #
251
#  needs:                                                                     #
252
#                                                                             #
253
#    $(PROJ).ncd                                                              #
254
#                                                                             #
255
#  created files: $(PROJ).bgn $(PROJ).bit $(PROJ).drc                         #
256
#                                                                             #
257
#    $(PROJ).bgn - human-readable BitGen report                               #
258
#    $(PROJ).drc - human readable DRC report                                  #
259
#    $(PROJ).bit - binary image file                                          #
260
#                                                                             #
261
###############################################################################
262
 
263
# We omit "-g StartUpClk:JtagClk" ; this doesn't work if the image is loaded
264
# from a PROM.
265
 
266
# Note: LCK_cycle:3 is non-standard
267
OPT_BITGEN = -w                     \
268
             -g DebugBitstream:No   \
269
             -g Binary:no           \
270
             -g CRC:Enable          \
271
             -g ConfigRate:6        \
272
             -g CclkPin:PullUp      \
273
             -g M0Pin:PullUp        \
274
             -g M1Pin:PullUp        \
275
             -g M2Pin:PullUp        \
276
             -g ProgPin:PullUp      \
277
             -g DonePin:PullUp      \
278
             -g TckPin:PullUp       \
279
             -g TdiPin:PullUp       \
280
             -g TdoPin:PullUp       \
281
             -g TmsPin:PullUp       \
282
             -g UnusedPin:PullDown  \
283
             -g UserID:0xFFFFFFFF   \
284
             -g DCMShutDown:Disable \
285
             -g DONE_cycle:4        \
286
             -g GTS_cycle:5         \
287
             -g GWE_cycle:6         \
288
             -g LCK_cycle:3         \
289
             -g Match_cycle:Auto    \
290
             -g Security:None       \
291
             -g DonePipe:No         \
292
             -g DriveDone:No
293
 
294
$(PROJ).bit $(PROJ).bgn $(PROJ).drc: $(PROJ).ncd
295
        bitgen $(OPT_INTSTYLE) $(OPT_BITGEN) $(PROJ).ncd
296
 
297
###############################################################################
298
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.