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[/] [spacewire_light/] [trunk/] [syn/] [streamtest_gr-xc3s1500/] [streamtest_top.vhd] - Blame information for rev 3

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1 3 jorisvr
--
2
--  Test of spwstream on Pender GR-XC3S-1500 board.
3
--  60 MHz system clock; 200 MHz receive clock and transmit clock.
4
--
5
--  LED 0 = link run
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--  LED 1 = link error (sticky until clear button)
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--  LED 2 = gotdata
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--  LED 3 = data/timecode error (sticky until reset)
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--
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--  Button S2 = reset
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--  Button S3 = clear LED 1
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--
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--  Switch 0 = link start
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--  Switch 1 = link disable
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--  Switch 2 = send data
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--  Switch 3 = send time codes
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--  Switch 4-7 = bits 0-3 of tx bit rate scale factor
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--
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--  SpaceWire signals on expansion connector J12:
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--    Data In    pos,neg  =  m1,m2  =  pin 3,2
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--    Strobe In  pos,neg  =  m3,m4  =  pin 6,5
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--    Data Out   pos,neg  =  n1,n2  =  pin 9,8
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--    Strobe Out pos,neg  =  n3,n4  =  pin 12,11
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--
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--  To get proper LVDS signals from connector J12, the voltage on I/O bank 6
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--  must be set to 2.5V. This is the default on GR-XC3S-1500-rev2, but on
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--  GR-XC3S-1500-rev1 a change is required on the board (described in
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--  the board manual).
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--
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--  To terminate the incoming LVDS signals, 100 Ohm termination resistors
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--  must be installed on the board in positions R120 and R121.
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--
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--  The SpaceWire port should be looped back to itself, either directly
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--  or via an other SpaceWire device. For a direct loopback, place 4 wires
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--  from the output pins to the corresponding input pins. For an indirect
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--  loopback, connect the SpaceWire signals to an additional SpaceWire device
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--  which is programmed to echo everything it receives (characters, packets,
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--  time codes). See the datasheet for a wiring diagram from J12 to MDM9.
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--
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41
library ieee;
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use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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use work.spwpkg.all;
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entity streamtest_top is
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    port (
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        clk:        in  std_logic;
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        btn_reset:  in  std_logic;
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        btn_clear:  in  std_logic;
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        switch:     in  std_logic_vector(7 downto 0);
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        led:        out std_logic_vector(3 downto 0);
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        spw_rxdp:   in  std_logic;
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        spw_rxdn:   in  std_logic;
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        spw_rxsp:   in  std_logic;
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        spw_rxsn:   in  std_logic;
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        spw_txdp:   out std_logic;
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        spw_txdn:   out std_logic;
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        spw_txsp:   out std_logic;
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        spw_txsn:   out std_logic );
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end entity streamtest_top;
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architecture streamtest_top_arch of streamtest_top is
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    -- Clock generation.
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    signal boardclk:        std_logic;
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    signal sysclk:          std_logic;
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    signal fastclk:         std_logic;
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    -- Synchronize buttons
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    signal s_resetbtn:      std_logic := '0';
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    signal s_clearbtn:      std_logic := '0';
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    -- Sticky LED
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    signal s_linkerrorled:  std_logic := '0';
79
 
80
    -- Interface signals.
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    signal s_rst:           std_logic := '1';
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    signal s_linkstart:     std_logic := '0';
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    signal s_autostart:     std_logic := '0';
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    signal s_linkdisable:   std_logic := '0';
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    signal s_senddata:      std_logic := '0';
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    signal s_sendtick:      std_logic := '0';
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    signal s_txdivcnt:      std_logic_vector(7 downto 0) := "00000000";
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    signal s_linkstarted:   std_logic;
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    signal s_linkconnecting: std_logic;
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    signal s_linkrun:       std_logic;
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    signal s_linkerror:     std_logic;
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    signal s_gotdata:       std_logic;
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    signal s_dataerror:     std_logic;
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    signal s_tickerror:     std_logic;
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    signal s_spwdi:         std_logic;
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    signal s_spwsi:         std_logic;
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    signal s_spwdo:         std_logic;
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    signal s_spwso:         std_logic;
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    -- Make clock nets visible to UCF file.
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    attribute KEEP: string;
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    attribute KEEP of sysclk: signal is "SOFT";
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    attribute KEEP of fastclk: signal is "SOFT";
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    component streamtest is
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        generic (
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            sysfreq:    real;
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            txclkfreq:  real;
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            tickdiv:    integer range 12 to 24 := 20;
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            rximpl:     spw_implementation_type := impl_generic;
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            rxchunk:    integer range 1 to 4 := 1;
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            tximpl:     spw_implementation_type := impl_generic;
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            rxfifosize_bits: integer range 6 to 14 := 11;
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            txfifosize_bits: integer range 2 to 14 := 11 );
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        port (
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            clk:        in  std_logic;
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            rxclk:      in  std_logic;
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            txclk:      in  std_logic;
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            rst:        in  std_logic;
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            linkstart:  in  std_logic;
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            autostart:  in  std_logic;
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            linkdisable: in std_logic;
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            senddata:   in  std_logic;
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            sendtick:   in  std_logic;
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            txdivcnt:   in  std_logic_vector(7 downto 0);
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            linkstarted: out std_logic;
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            linkconnecting: out std_logic;
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            linkrun:    out std_logic;
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            linkerror:  out std_logic;
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            gotdata:    out std_logic;
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            dataerror:  out std_logic;
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            tickerror:  out std_logic;
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            spw_di:     in  std_logic;
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            spw_si:     in  std_logic;
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            spw_do:     out std_logic;
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            spw_so:     out std_logic );
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    end component;
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begin
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    -- Buffer incoming clock.
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    bufg0: BUFG port map ( I => clk, O => boardclk );
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    -- Generate 60 MHz system clock.
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    dcm0: DCM
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        generic map (
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            CLKFX_DIVIDE        => 5,
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            CLKFX_MULTIPLY      => 6,
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            CLK_FEEDBACK        => "NONE",
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            CLKIN_DIVIDE_BY_2   => false,
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            CLKIN_PERIOD        => 20.0,
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            CLKOUT_PHASE_SHIFT  => "NONE",
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            DESKEW_ADJUST       => "SYSTEM_SYNCHRONOUS",
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            DFS_FREQUENCY_MODE  => "LOW",
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            DUTY_CYCLE_CORRECTION => true,
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            STARTUP_WAIT        => true )
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        port map (
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            CLKIN       => boardclk,
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            RST         => '0',
160
            CLKFX       => sysclk );
161
 
162
    -- Generate 200 MHz fast clock.
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    dcm1: DCM
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        generic map (
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            CLKFX_DIVIDE        => 1,
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            CLKFX_MULTIPLY      => 4,
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            CLK_FEEDBACK        => "NONE",
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            CLKIN_DIVIDE_BY_2   => false,
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            CLKIN_PERIOD        => 20.0,
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            CLKOUT_PHASE_SHIFT  => "NONE",
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            DESKEW_ADJUST       => "SYSTEM_SYNCHRONOUS",
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            DFS_FREQUENCY_MODE  => "LOW",
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            DUTY_CYCLE_CORRECTION => true,
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            STARTUP_WAIT        => true )
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        port map (
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            CLKIN       => boardclk,
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            RST         => '0',
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            CLKFX       => fastclk );
179
 
180
    -- Streamtest instance
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    streamtest_inst: streamtest
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        generic map (
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            sysfreq     => 60.0e6,
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            txclkfreq   => 200.0e6,
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            tickdiv     => 22,
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            rximpl      => impl_fast,
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            rxchunk     => 4,
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            tximpl      => impl_fast,
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            rxfifosize_bits => 11,
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            txfifosize_bits => 10 )
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        port map (
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            clk         => sysclk,
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            rxclk       => fastclk,
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            txclk       => fastclk,
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            rst         => s_rst,
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            linkstart   => s_linkstart,
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            autostart   => s_autostart,
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            linkdisable => s_linkdisable,
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            senddata    => s_senddata,
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            sendtick    => s_sendtick,
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            txdivcnt    => s_txdivcnt,
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            linkstarted => s_linkstarted,
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            linkconnecting => s_linkconnecting,
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            linkrun     => s_linkrun,
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            linkerror   => s_linkerror,
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            gotdata     => s_gotdata,
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            dataerror   => s_dataerror,
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            tickerror   => s_tickerror,
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            spw_di      => s_spwdi,
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            spw_si      => s_spwsi,
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            spw_do      => s_spwdo,
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            spw_so      => s_spwso );
213
 
214
    -- LVDS buffers
215
    spwdi_pad: IBUFDS
216
        generic map ( IOSTANDARD => "LVDS_25" )
217
        port map ( O => s_spwdi, I => spw_rxdp, IB => spw_rxdn );
218
    spwsi_pad: IBUFDS
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        generic map ( IOSTANDARD => "LVDS_25" )
220
        port map ( O => s_spwsi, I => spw_rxsp, IB => spw_rxsn );
221
    spwdo_pad: OBUFDS
222
        generic map ( IOSTANDARD => "LVDS_25" )
223
        port map ( O => spw_txdp, OB => spw_txdn, I => s_spwdo );
224
    spwso_pad: OBUFDS
225
        generic map ( IOSTANDARD => "LVDS_25" )
226
        port map ( O => spw_txsp, OB => spw_txsn, I => s_spwso );
227
 
228
    process (sysclk) is
229
    begin
230
        if rising_edge(sysclk) then
231
 
232
            -- Synchronize buttons
233
            s_resetbtn  <= btn_reset;
234
            s_rst       <= s_resetbtn;
235
            s_clearbtn  <= btn_clear;
236
 
237
            -- Synchronize switch settings
238
            s_autostart <= '0';
239
            s_linkstart <= switch(0);
240
            s_linkdisable <= switch(1);
241
            s_senddata  <= switch(2);
242
            s_sendtick  <= switch(3);
243
            s_txdivcnt(3 downto 0) <= switch(7 downto 4);
244
 
245
            -- Sticky link error LED
246
            s_linkerrorled <= (s_linkerrorled or s_linkerror) and
247
                              (not s_clearbtn) and
248
                              (not s_resetbtn);
249
 
250
            -- Drive LEDs (inverted logic)
251
            led(0)  <= not s_linkrun;
252
            led(1)  <= not s_linkerrorled;
253
            led(2)  <= not s_gotdata;
254
            led(3)  <= not (s_dataerror or s_tickerror);
255
 
256
        end if;
257
    end process;
258
 
259
end architecture streamtest_top_arch;

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