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[/] [special_functions_unit/] [Open_source_SFU/] [cordic_vhdl/] [parts/] [multFP.vhd] - Blame information for rev 4

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1 4 divadnauj
-- multiplicador Ripple Carry.
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Library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity multFP is
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port(
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        entrada_x, entrada_y: in std_logic_vector(31 downto 0);
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        salida: out std_logic_vector(31 downto 0);
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        underflow, overflow :out std_logic
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        );
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end multFP;
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architecture ar of multFP is
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type desplazar is array(0 to 47) of std_logic_vector(47 downto 0);
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signal mantisa_finalex :desplazar :=(others=>(others=>'0'));
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signal mantisa1_n,mantisa2_n :std_logic_vector(23 downto 0);
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signal mantisa_final :std_logic_vector(47 downto 0);
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signal mantisa_real :std_logic_vector(22 downto 0);
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signal resultado :std_logic_vector(31 downto 0);
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signal exponente_final :std_logic_vector(9 downto 0);
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signal exponentex,exponentey :std_logic_vector(9 downto 0);
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signal sunderflow, soverflow :std_logic;
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begin
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-- Se suman exponentes:
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--exponente_final(7 downto 0) contiene el exponente listo.
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mantisa1_n <= '1' & entrada_x(22 downto 0);                              -- inclusion de 1 en el bit mas significativo para multiplicacion. 
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mantisa2_n <= '1' & entrada_y(22 downto 0);
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exponentex <= "00"& entrada_x(30 downto 23);
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exponentey <= "00"& entrada_y(30 downto 23);
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-- operacion sobre la mantisa.          
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mantisa_final<=std_logic_vector(unsigned(mantisa1_n)*unsigned(mantisa2_n));
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process(entrada_x,entrada_y,resultado,sunderflow,soverflow)
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begin
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if unsigned(entrada_x) = X"00000000" or unsigned(entrada_y) = X"00000000" or unsigned(entrada_x) = X"80000000" or unsigned(entrada_y) = X"80000000"  then -- no se realiza la operacion, uno de los operandos es cero por lo tanto la respuesta es cero.
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        salida <= (others=>'0');
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        underflow <='0';
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        overflow <= '0';
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else                                            -- se realiza la operacion.
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        underflow<=sunderflow;
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        overflow<= soverflow;
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        salida <= resultado;
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        salida(31)<= (entrada_x(31) xor entrada_y(31));  -- asignacion de signo al resultado.
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end if;
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end process;
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process(mantisa_final,exponentex,exponentey)
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begin
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        if(mantisa_final(47)='1') then
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                exponente_final <= std_logic_vector((unsigned(exponentex) + unsigned(exponentey)) - 126);
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        else
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                exponente_final <= std_logic_vector((unsigned(exponentex) + unsigned(exponentey)) - 127);
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        end if;
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end process;
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process(exponente_final,mantisa_real)
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begin
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if signed(exponente_final) > 255 then                   -- finaliza la operacion si hay overflow.
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        soverflow<='1';
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        sunderflow<='0';
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        resultado <= (others=>'0');
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elsif   signed(exponente_final) < 0 then                 -- finaliza la operacion si hay underflow.
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        sunderflow<='1';
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        soverflow<='0';
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        resultado <= (others=>'0');
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else                                                                                    -- continue con la operacion.           
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        sunderflow<='0';
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        soverflow<='0';
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        -- asignacion final del resultado.
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        resultado(22 downto 0) <= mantisa_real;          -- Mantisa.
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        resultado(30 downto 23) <= exponente_final(7 downto 0);  -- Exponente.
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end if;
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end process;
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mantisa_finalex(47) <= mantisa_final;
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NX:for i in 46 downto 0 generate
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        mantisa_finalex(i) <= mantisa_finalex(i+1)(46 downto 0) & '0';
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end generate;
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process(mantisa_final,mantisa_finalex)
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variable var :integer;
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begin
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var:=0;
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for i in 0 to 47 loop
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        if(mantisa_final(i)='1') then
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                var:=i;
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        end if;
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end loop;
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mantisa_real <= mantisa_finalex(var)(46 downto 24);
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end process;
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end ar;

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