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[/] [special_functions_unit/] [Open_source_SFU/] [cordic_vhdl/] [parts/] [mux2_1.vhd] - Blame information for rev 4

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1 4 divadnauj
library IEEE;
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use ieee.std_logic_1164.all;
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entity mux2_1 is
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port(
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         x,y,s: in std_logic;
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         z: out std_logic
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        );
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end mux2_1;
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architecture au of mux2_1 is
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begin
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z <= x when s='0' else y when s='1';  -- si S=1 salida =y, si S=0 salida =X
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end au;

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