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[/] [special_functions_unit/] [Open_source_SFU/] [cordic_vhdl/] [parts/] [mux2_1.vhd] - Blame information for rev 4

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library IEEE;
use ieee.std_logic_1164.all;
 
entity mux2_1 is
port(
         x,y,s: in std_logic;
         z: out std_logic
        );
end mux2_1;
 
architecture au of mux2_1 is
begin
z <= x when s='0' else y when s='1';  -- si S=1 salida =y, si S=0 salida =X
end au;

Line No.	Rev	Author	Line
1	4	divadnauj	`library IEEE;`
2			`use ieee.std_logic_1164.all;`
3
4			`entity mux2_1 is`
5			`port(`
6			`x,y,s: in std_logic;`
7			`z: out std_logic`
8			`);`
9			`end mux2_1;`
10
11			`architecture au of mux2_1 is`
12			`begin`
13			`z <= x when s='0' else y when s='1'; -- si S=1 salida =y, si S=0 salida =X`
14			`end au;`

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[/] [special_functions_unit/] [Open_source_SFU/] [cordic_vhdl/] [parts/] [mux2_1.vhd] - Blame information for rev 4