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[/] [special_functions_unit/] [Open_source_SFU/] [cordic_vhdl/] [parts/] [punto1.vhd] - Blame information for rev 4

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1 4 divadnauj
-- barrel shifter.
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-- desplazamiento izquierdo.
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Library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity punto1 is
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generic(
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                long : natural := 64;
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                v1:natural := 2;
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                v2:natural := 4;
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                v3:natural := 8;
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                v4:natural := 16;
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                bass : natural := 2
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                );
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port(
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        entrada_real: in unsigned(long-1 downto 0);
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        shift: in unsigned(6 downto 0);
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        salida_real: out unsigned(23 downto 0)
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        );
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end punto1;
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architecture ar of punto1 is
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    type vector is array (0 to 5,0 to long-1) of std_logic;       -- (0 a log de # bits, long de Bit)
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    signal var: vector;
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    signal entrada, salida,salida_inv: unsigned(long-1 downto 0);
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        component mux2_1 is
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        port(
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                x,y,s: in  std_logic;
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                z: out std_logic
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                );
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        end component;
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        type vec is array (0 to 7) of natural;
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        signal basse: vec :=(v1 ,v2 ,v3 ,v4 ,8 ,16 ,32 ,64);
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begin
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                -- agregado para hacer inversion de dato de entrada.
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                ENTRADAX:for i in 0 to long-1 generate
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                        entrada(i)<= entrada_real(long-1-i);
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                        salida_inv(i)<= salida(long-1-i);
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                end generate;
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                SALIDAX:for i in 0 to 23 generate                -- para esta aplicacion solo se tomas los 23 datos.
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                        salida_real(i)<= salida_inv(i);
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                end generate;
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            GENX:for i in 0 to long-1 generate
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                        PART_B: if i< 1 generate
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                        MU: mux2_1 port map(
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                                                                x=>entrada(0),
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                                                                y=>'0',
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                                                                s=>shift(0),
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                                                                z=>var(0,0)
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                                                                );
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                        end generate PART_B;
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                        PART_A: if i >= 1 generate
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                        MU: mux2_1 port map(x=>entrada(i),
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                                                                y=>entrada(i-1),
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                                                                s=>shift(0),
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                                                                z=>var(0,i)
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                                                                );
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                        end generate PART_A;
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                end generate GENX;
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                --capa 2                
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        GENA:for i in 0 to long-1 generate
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                PART_B1: if i < 2 generate
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                        MX0:mux2_1 port map(x=>var(0,i),
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                                                                y=>'0',
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                                                                s=>shift(1),
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                                                                z=>var(1,i)
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                                                                );
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                end generate PART_B1;
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                PART_A1: if i >= 2 generate
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                        MY: mux2_1 port map(x=>var(0,i),
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                                        y=>var(0,i-2),
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                                        s=>shift(1),
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                                    z=>var(1,i)
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                                        );
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                end generate PART_A1;
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        end generate GENA;
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                --capa 3
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        GENA1:for i in 0 to long-1 generate
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                PART_B1: if i < 4 generate
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                        MX0:mux2_1 port map(x=>var(1,i),
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                                                                y=>'0',
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                                                                s=>shift(2),
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                                                                z=>var(2,i)
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                                                                );
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                end generate PART_B1;
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                PART_A1: if i >= 4 generate
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                        MY: mux2_1 port map(x=>var(1,i),
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                                        y=>var(1,i-4),
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                                        s=>shift(2),
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                                    z=>var(2,i)
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                                        );
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                end generate PART_A1;
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        end generate GENA1;
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        --capa 4
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        GENA2:for i in 0 to long-1 generate
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                PART_B1: if i < 8 generate
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                        MX0:mux2_1 port map(x=>var(2,i),
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                                                                y=>'0',
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                                                                s=>shift(3),
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                                                                z=>var(3,i)
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                                                                );
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                end generate PART_B1;
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                PART_A1: if i >= 8 generate
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                        MY: mux2_1 port map(x=>var(2,i),
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                                        y=>var(2,i-8),
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                                        s=>shift(3),
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                                    z=>var(3,i)
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                                        );
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                end generate PART_A1;
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        end generate GENA2;
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                --capa5
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        GENA3:for i in 0 to long-1 generate
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                PART_B1: if i < 16 generate
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                        MX0:mux2_1 port map(x=>var(3,i),
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                                                                y=>'0',
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                                                                s=>shift(4),
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                                                                z=>var(4,i)
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                                                                );
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                end generate PART_B1;
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                PART_A1: if i >= 16 generate
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                        MY: mux2_1 port map(x=>var(3,i),
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                                        y=>var(3,i-16),
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                                        s=>shift(4),
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                                    z=>var(4,i)
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                                        );
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                end generate PART_A1;
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        end generate GENA3;
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                --capa 6
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        GENB:for i in 0 to long-1 generate
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                PART_Bx: if i < 32 generate
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                MW0:mux2_1 port map(x=>var(4,i),
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                                        y=>'0',
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                                        s=>shift(5),
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                                    z=>salida(i)
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                                        );
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                end generate PART_Bx;
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                PART_Ax: if i >= 32 generate
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                MZ: mux2_1 port map(x=>var(4,i),
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                                        y=>var(4,i-32),
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                                        s=>shift(5),
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                                    z=>salida(i)
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                                        );
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                end generate PART_Ax;
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        end generate GENB;
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end ar;

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