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[/] [special_functions_unit/] [Open_source_SFU/] [cordic_vhdl/] [parts/] [punto1.vhd] - Blame information for rev 4

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-- barrel shifter.
-- desplazamiento izquierdo.
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity punto1 is
generic(
                long : natural := 64;
                v1:natural := 2;
                v2:natural := 4;
                v3:natural := 8;
                v4:natural := 16;
                bass : natural := 2
                );
 
port(
        entrada_real: in unsigned(long-1 downto 0);
        shift: in unsigned(6 downto 0);
        salida_real: out unsigned(23 downto 0)
        );
end punto1;
 
architecture ar of punto1 is
 
    type vector is array (0 to 5,0 to long-1) of std_logic;       -- (0 a log de # bits, long de Bit)
    signal var: vector;
    signal entrada, salida,salida_inv: unsigned(long-1 downto 0);
 
        component mux2_1 is
        port(
                x,y,s: in  std_logic;
                z: out std_logic
                );
        end component;
 
        type vec is array (0 to 7) of natural;
        signal basse: vec :=(v1 ,v2 ,v3 ,v4 ,8 ,16 ,32 ,64);
 
begin
 
                -- agregado para hacer inversion de dato de entrada.
 
                ENTRADAX:for i in 0 to long-1 generate
                        entrada(i)<= entrada_real(long-1-i);
                        salida_inv(i)<= salida(long-1-i);
                end generate;
 
                SALIDAX:for i in 0 to 23 generate                -- para esta aplicacion solo se tomas los 23 datos.
                        salida_real(i)<= salida_inv(i);
                end generate;
 
 
 
            GENX:for i in 0 to long-1 generate
 
                        PART_B: if i< 1 generate
                        MU: mux2_1 port map(
                                                                x=>entrada(0),
                                                                y=>'0',
                                                                s=>shift(0),
                                                                z=>var(0,0)
                                                                );
                        end generate PART_B;
 
                        PART_A: if i >= 1 generate
                        MU: mux2_1 port map(x=>entrada(i),
                                                                y=>entrada(i-1),
                                                                s=>shift(0),
                                                                z=>var(0,i)
                                                                );
                        end generate PART_A;
 
                end generate GENX;
 
                --capa 2                
 
        GENA:for i in 0 to long-1 generate
 
                PART_B1: if i < 2 generate
                        MX0:mux2_1 port map(x=>var(0,i),
                                                                y=>'0',
                                                                s=>shift(1),
                                                                z=>var(1,i)
                                                                );
                end generate PART_B1;
 
                PART_A1: if i >= 2 generate
                        MY: mux2_1 port map(x=>var(0,i),
                                        y=>var(0,i-2),
                                        s=>shift(1),
                                    z=>var(1,i)
                                        );
                end generate PART_A1;
        end generate GENA;
 
 
                --capa 3
 
 
        GENA1:for i in 0 to long-1 generate
 
                PART_B1: if i < 4 generate
                        MX0:mux2_1 port map(x=>var(1,i),
                                                                y=>'0',
                                                                s=>shift(2),
                                                                z=>var(2,i)
                                                                );
                end generate PART_B1;
 
                PART_A1: if i >= 4 generate
                        MY: mux2_1 port map(x=>var(1,i),
                                        y=>var(1,i-4),
                                        s=>shift(2),
                                    z=>var(2,i)
                                        );
                end generate PART_A1;
        end generate GENA1;
 
        --capa 4
 
        GENA2:for i in 0 to long-1 generate
 
                PART_B1: if i < 8 generate
                        MX0:mux2_1 port map(x=>var(2,i),
                                                                y=>'0',
                                                                s=>shift(3),
                                                                z=>var(3,i)
                                                                );
                end generate PART_B1;
 
                PART_A1: if i >= 8 generate
                        MY: mux2_1 port map(x=>var(2,i),
                                        y=>var(2,i-8),
                                        s=>shift(3),
                                    z=>var(3,i)
                                        );
                end generate PART_A1;
        end generate GENA2;
 
                --capa5
        GENA3:for i in 0 to long-1 generate
 
                PART_B1: if i < 16 generate
                        MX0:mux2_1 port map(x=>var(3,i),
                                                                y=>'0',
                                                                s=>shift(4),
                                                                z=>var(4,i)
                                                                );
                end generate PART_B1;
 
                PART_A1: if i >= 16 generate
                        MY: mux2_1 port map(x=>var(3,i),
                                        y=>var(3,i-16),
                                        s=>shift(4),
                                    z=>var(4,i)
                                        );
                end generate PART_A1;
        end generate GENA3;
 
                --capa 6
        GENB:for i in 0 to long-1 generate
 
                PART_Bx: if i < 32 generate
 
                MW0:mux2_1 port map(x=>var(4,i),
                                        y=>'0',
                                        s=>shift(5),
                                    z=>salida(i)
                                        );
 
                end generate PART_Bx;
 
                PART_Ax: if i >= 32 generate
 
                MZ: mux2_1 port map(x=>var(4,i),
                                        y=>var(4,i-32),
                                        s=>shift(5),
                                    z=>salida(i)
                                        );
                end generate PART_Ax;
        end generate GENB;
end ar;

Line No.	Rev	Author	Line
1	4	divadnauj	`-- barrel shifter.`
2			`-- desplazamiento izquierdo.`
3			`Library IEEE;`
4			`use ieee.std_logic_1164.all;`
5			`use ieee.numeric_std.all;`
6
7			`entity punto1 is`
8			`generic(`
9			`long : natural := 64;`
10			`v1:natural := 2;`
11			`v2:natural := 4;`
12			`v3:natural := 8;`
13			`v4:natural := 16;`
14			`bass : natural := 2`
15			`);`
16
17			`port(`
18			`entrada_real: in unsigned(long-1 downto 0);`
19			`shift: in unsigned(6 downto 0);`
20			`salida_real: out unsigned(23 downto 0)`
21			`);`
22			`end punto1;`
23
24			`architecture ar of punto1 is`
25
26			`type vector is array (0 to 5,0 to long-1) of std_logic; -- (0 a log de # bits, long de Bit)`
27			`signal var: vector;`
28			`signal entrada, salida,salida_inv: unsigned(long-1 downto 0);`
29
30			`component mux2_1 is`
31			`port(`
32			`x,y,s: in std_logic;`
33			`z: out std_logic`
34			`);`
35			`end component;`
36
37			`type vec is array (0 to 7) of natural;`
38			`signal basse: vec :=(v1 ,v2 ,v3 ,v4 ,8 ,16 ,32 ,64);`
39
40			`begin`
41
42			`-- agregado para hacer inversion de dato de entrada.`
43
44			`ENTRADAX:for i in 0 to long-1 generate`
45			`entrada(i)<= entrada_real(long-1-i);`
46			`salida_inv(i)<= salida(long-1-i);`
47			`end generate;`
48
49			`SALIDAX:for i in 0 to 23 generate -- para esta aplicacion solo se tomas los 23 datos.`
50			`salida_real(i)<= salida_inv(i);`
51			`end generate;`
52
53
54
55			`GENX:for i in 0 to long-1 generate`
56
57			`PART_B: if i< 1 generate`
58			`MU: mux2_1 port map(`
59			`x=>entrada(0),`
60			`y=>'0',`
61			`s=>shift(0),`
62			`z=>var(0,0)`
63			`);`
64			`end generate PART_B;`
65
66			`PART_A: if i >= 1 generate`
67			`MU: mux2_1 port map(x=>entrada(i),`
68			`y=>entrada(i-1),`
69			`s=>shift(0),`
70			`z=>var(0,i)`
71			`);`
72			`end generate PART_A;`
73
74			`end generate GENX;`
75
76			`--capa 2`
77
78			`GENA:for i in 0 to long-1 generate`
79
80			`PART_B1: if i < 2 generate`
81			`MX0:mux2_1 port map(x=>var(0,i),`
82			`y=>'0',`
83			`s=>shift(1),`
84			`z=>var(1,i)`
85			`);`
86			`end generate PART_B1;`
87
88			`PART_A1: if i >= 2 generate`
89			`MY: mux2_1 port map(x=>var(0,i),`
90			`y=>var(0,i-2),`
91			`s=>shift(1),`
92			`z=>var(1,i)`
93			`);`
94			`end generate PART_A1;`
95			`end generate GENA;`
96
97
98			`--capa 3`
99
100
101			`GENA1:for i in 0 to long-1 generate`
102
103			`PART_B1: if i < 4 generate`
104			`MX0:mux2_1 port map(x=>var(1,i),`
105			`y=>'0',`
106			`s=>shift(2),`
107			`z=>var(2,i)`
108			`);`
109			`end generate PART_B1;`
110
111			`PART_A1: if i >= 4 generate`
112			`MY: mux2_1 port map(x=>var(1,i),`
113			`y=>var(1,i-4),`
114			`s=>shift(2),`
115			`z=>var(2,i)`
116			`);`
117			`end generate PART_A1;`
118			`end generate GENA1;`
119
120			`--capa 4`
121
122			`GENA2:for i in 0 to long-1 generate`
123
124			`PART_B1: if i < 8 generate`
125			`MX0:mux2_1 port map(x=>var(2,i),`
126			`y=>'0',`
127			`s=>shift(3),`
128			`z=>var(3,i)`
129			`);`
130			`end generate PART_B1;`
131
132			`PART_A1: if i >= 8 generate`
133			`MY: mux2_1 port map(x=>var(2,i),`
134			`y=>var(2,i-8),`
135			`s=>shift(3),`
136			`z=>var(3,i)`
137			`);`
138			`end generate PART_A1;`
139			`end generate GENA2;`
140
141			`--capa5`
142			`GENA3:for i in 0 to long-1 generate`
143
144			`PART_B1: if i < 16 generate`
145			`MX0:mux2_1 port map(x=>var(3,i),`
146			`y=>'0',`
147			`s=>shift(4),`
148			`z=>var(4,i)`
149			`);`
150			`end generate PART_B1;`
151
152			`PART_A1: if i >= 16 generate`
153			`MY: mux2_1 port map(x=>var(3,i),`
154			`y=>var(3,i-16),`
155			`s=>shift(4),`
156			`z=>var(4,i)`
157			`);`
158			`end generate PART_A1;`
159			`end generate GENA3;`
160
161			`--capa 6`
162			`GENB:for i in 0 to long-1 generate`
163
164			`PART_Bx: if i < 32 generate`
165
166			`MW0:mux2_1 port map(x=>var(4,i),`
167			`y=>'0',`
168			`s=>shift(5),`
169			`z=>salida(i)`
170			`);`
171
172			`end generate PART_Bx;`
173
174			`PART_Ax: if i >= 32 generate`
175
176			`MZ: mux2_1 port map(x=>var(4,i),`
177			`y=>var(4,i-32),`
178			`s=>shift(5),`
179			`z=>salida(i)`
180			`);`
181			`end generate PART_Ax;`
182			`end generate GENB;`
183			`end ar;`

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[/] [special_functions_unit/] [Open_source_SFU/] [cordic_vhdl/] [parts/] [punto1.vhd] - Blame information for rev 4