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[/] [special_functions_unit/] [Open_source_SFU/] [log2_vhdl/] [parts/] [FA.vhd] - Blame information for rev 4

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1 4 divadnauj
-- FULL ADDER
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-- universidad Pedagogica y Tecnologica de Colombia.
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-- Facultad de ingenieria.
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-- Escuela de ingenieria Electronica - extension Tunja.
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-- Semillero de investigacion DDA y PDI
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-- Autor: Cristhian Fernando Moreno Manrique
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-------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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-------------------------------------------------------
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entity FA is
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        port(
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                i_term1 :in std_logic;
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                i_term2 :in std_logic;
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                i_cin           :in std_logic;
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                o_sum           :out std_logic;
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                o_cout  :out std_logic
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        );
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end entity;
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-------------------------------------------------------                         
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architecture main of FA is
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        signal s_xor: std_logic;
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begin
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        s_xor           <= i_term1 xor i_term2;
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        o_cout  <= (i_term1 and i_term2) or (i_cin and s_xor);
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        o_sum   <=  s_xor xor i_cin;
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----    option 2:
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--      o_cout  <= (i_term1 and i_term2) or (i_term1 and i_cin) or (i_term2 and i_cin);
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--      o_sum   <= i_term1 xor i_term2 xor i_cin;
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end main;
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-------------------------------------------------------

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