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[/] [special_functions_unit/] [Open_source_SFU/] [log2_vhdl/] [parts/] [comparator.vhd] - Blame information for rev 4

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1 4 divadnauj
-- Nombre de archivo    : comparator.vhd
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--      Titulo                          : comparador de magnitud configurable
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-----------------------------------------------------------------------------   
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-- Descripcion                  : compara dos datos de entrada segun el modo seleccionado
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--
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--      WIDE                            : numero de bits de los numeros a comparar
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--              MODO                            : 2 -> i_data1 < i_data2
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--                                                        1 -> i_data1 > i_data2
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--                                                        0 -> i_data1 = i_data2
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--
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--      i_term1                 : Numero 1
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--      i_term2                 : Numero 2
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--      o_result                        : Resultado
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--
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-----------------------------------------------------------------------------   
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-- Universidad Pedagogica y Tecnologica de Colombia.
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-- Facultad de ingenieria.
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-- Escuela de ingenieria Electronica - extension Tunja.
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-- 
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-- Autor: Cristhian Fernando Moreno Manrique
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-- Marzo 2020
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-----------------------------------------------------------------------------   
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library ieee;
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        use ieee.std_logic_1164.all;
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entity comparator is
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        generic (WIDE           :               natural:=       8;
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                                MODO            :               natural:=       0);
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        port      (i_data1      : in    std_logic_vector(WIDE-1 downto 0);
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                                i_data2 : in    std_logic_vector(WIDE-1 downto 0);
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                                o_result        : out std_logic);
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end entity;
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-----------------------------------------------------------------------------   
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architecture main of comparator is
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begin
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        EQ: if (MODO = 0) generate
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                o_result <= '1' when (i_data1 = i_data2) else '0';
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        end generate;
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        HG: if (MODO = 1) generate
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                o_result <= '1' when (i_data1 > i_data2) else '0';
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        end generate;
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        LW: if (MODO > 1) generate
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                o_result <= '1' when (i_data1 < i_data2) else '0';
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        end generate;
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end main;
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-----------------------------------------------------------------------------   

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