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[/] [special_functions_unit/] [Open_source_SFU/] [log2_vhdl/] [parts/] [log2_ieee.vhd] - Blame information for rev 4

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1 4 divadnauj
-- Log2 IEEE754 case detect
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library ieee;
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        use ieee.std_logic_1164.all;
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        use ieee.numeric_std.all;
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entity log2_ieee is
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        port      (i_data                                       : in    std_logic_vector(31 downto 0);
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                                o_case                                  : out std_logic_vector(31 downto 0);
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                                o_case_en                               : out std_logic);
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end entity;
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architecture rtl of log2_ieee is
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        signal s_sgn    : std_logic;
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        signal s_exp    : std_logic_vector(7 downto 0);
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        signal s_mantis: std_logic_vector(22 downto 0);
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begin
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        s_sgn <= i_data(i_data'left);
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        s_exp <= i_data(i_data'left-1 downto 23);
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        s_mantis        <= i_data(22 downto 0);
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        process(s_sgn, s_exp, s_mantis)
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        begin
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                if s_exp = X"00" then
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                        o_case          <= X"FF800000";
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                        o_case_en       <= '1';
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                elsif s_exp = X"FF" then
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                        o_case_en       <= '1';
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                        if s_sgn = '0' and s_mantis = "00000000000000000000000" then
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                                o_case <= X"7F800000";
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                        else
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                                o_case <= X"FFFFFFFF";
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                        end if;
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                elsif   s_exp = X"7F" and s_mantis = "00000000000000000000000" and s_sgn = '0' then
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                        o_case_en       <= '1';
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                        o_case <= X"00000000";
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                elsif s_sgn = '1' then
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                        o_case_en       <= '1';
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                        o_case <= X"FFFFFFFF";
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                else
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                        o_case_en       <= '0';
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                        o_case <= X"00000000";
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                end if;
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        end process;
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end rtl;
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