OpenCores
URL https://opencores.org/ocsvn/special_functions_unit/special_functions_unit/trunk

Subversion Repositories special_functions_unit

[/] [special_functions_unit/] [Open_source_SFU/] [log2_vhdl/] [parts/] [mult.vhd] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 divadnauj
-- multiplicador descripcion estructural
2
library ieee;
3
        use ieee.std_logic_1164.all;
4
        use ieee.numeric_std.all;
5
 
6
entity mult is
7
        generic (WIDE                   :               natural := 8);
8
        port      (i_term1              : in    std_logic_vector(WIDE-1 downto 0);
9
                                i_term2         : in    std_logic_vector(WIDE-1 downto 0);
10
                                o_product       : out   std_logic_vector(WIDE*2-1 downto 0));
11
end entity;
12
 
13
 
14
architecture rtl of mult is
15
        signal s_term1: integer;
16
        signal s_term2: integer;
17
 
18
        type array_terms is array (WIDE-1 downto 0) of std_logic_vector(WIDE-1 downto 0);
19
        signal w_and_terms: array_terms;
20
 
21
        signal w_terms1: array_terms;
22
        signal w_terms2: array_terms;
23
 
24
        signal w_FAcin: array_terms;
25
 
26
        --signal w_HAterm1: std_logic_vector(WIDE-2 downto 0);
27
        --signal w_HAterm2: std_logic_vector(WIDE-2 downto 0);
28
        signal w_HAcout: std_logic_vector(WIDE-2 downto 0);
29
        signal w_HAresult: std_logic_vector(WIDE-2 downto 0);
30
begin
31
        --(i)columnas(j)filas
32
        w_terms1(0) <= "0" & w_and_terms(0)(WIDE-1 downto 1);
33
 
34
 
35
        U_i: for i in 0 to WIDE-1 generate
36
                U_j: for j in 0 to WIDE-1 generate
37
                        w_and_terms(i)(j) <= i_term1(j) and i_term2(i);
38
 
39
                        UU_i: if i < WIDE-1 generate
40
                                w_terms2(i)             <= w_and_terms(i+1);
41
 
42
--                              Half Adders
43
                                U_HA: if j = 0 generate
44
                                        w_HAcout(i)             <= w_terms1(i)(0) and w_terms2(i)(0);
45
                                        w_HAresult(i)   <= w_terms1(i)(0) xor w_terms2(i)(0);
46
                                        w_FAcin(i)(0) <= w_HAcout(i);
47
                                end generate;
48
 
49
                                U_FA: if j /= 0 generate
50
                                        a: entity work.FA port map(
51
                                                i_term1 => w_terms1(i)(j),
52
                                                i_term2 => w_terms2(i)(j),
53
                                                i_cin           => w_FAcin(i)(j-1),
54
                                                o_Sum   => w_terms1(i+1)(j-1),
55
                                                o_cout  => w_FAcin(i)(j)
56
                                        );
57
                                end generate;
58
 
59
                                UU: if j = WIDE-1 generate
60
                                        w_terms1(i+1)(j) <= w_FAcin(i)(j);
61
                                end generate;
62
 
63
                                o_product(i+1)  <= w_HAresult(i);
64
                        end generate;
65
 
66
                end generate;
67
 
68
        end generate;
69
 
70
        o_product(0) <= w_and_terms(0)(0);
71
        o_product(o_product'left downto WIDE) <= w_terms1(WIDE-1)(WIDE-1 downto 0);
72
end rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.