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jdoin |
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-- Company:
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-- Engineer: Jonny Doin
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--
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-- Create Date: 22:59:18 04/25/2011
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-- Design Name: spi_master_slave
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-- Module Name: spi_master_slave/spi_loopback_test.vhd
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-- Project Name: SPI_interface
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-- Target Device: Spartan-6
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-- Tool versions: ISE 13.1
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-- Description: Testbench to simulate the master and slave SPI interfaces. Each module can be tested
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-- in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave'
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-- module, simulating the internal working of each design.
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-- In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for
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-- both modules, and also a different clock domain for each parallel interface.
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-- Different values for PREFETCH for each interface can be tested, to model the best value
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-- for the pipelined memory / bus that is attached to the di/do ports.
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-- To test the parallel interfaces, a simple ROM memory is simulated for each interface, with
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-- 8 words of data to be sent, synchronous to each clock and flow control signals.
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--
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--
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-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave'
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.10 - Implemented FIFO simulation for each interface.
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.all;
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ENTITY spi_loopback_test IS
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GENERIC (
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N : positive := 32; -- 32bit serial word length is default
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CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
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CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
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PREFETCH : positive := 2 -- prefetch lookahead cycles
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);
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END spi_loopback_test;
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ARCHITECTURE behavior OF spi_loopback_test IS
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--=========================================================
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-- Component declaration for the Unit Under Test (UUT)
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--=========================================================
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COMPONENT spi_loopback
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PORT(
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m_clk_i : IN std_logic;
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m_rst_i : IN std_logic;
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m_spi_miso_i : IN std_logic;
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m_di_i : IN std_logic_vector(31 downto 0);
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m_wren_i : IN std_logic;
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s_clk_i : IN std_logic;
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s_spi_ssel_i : IN std_logic;
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s_spi_sck_i : IN std_logic;
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s_spi_mosi_i : IN std_logic;
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s_di_i : IN std_logic_vector(31 downto 0);
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s_wren_i : IN std_logic;
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m_spi_ssel_o : OUT std_logic;
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m_spi_sck_o : OUT std_logic;
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m_spi_mosi_o : OUT std_logic;
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m_di_req_o : OUT std_logic;
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m_do_valid_o : OUT std_logic;
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m_do_o : OUT std_logic_vector(31 downto 0);
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m_do_transfer_o : OUT std_logic;
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m_wren_o : OUT std_logic;
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m_wren_ack_o : OUT std_logic;
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m_rx_bit_reg_o : OUT std_logic;
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m_state_dbg_o : OUT std_logic_vector(5 downto 0);
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m_core_clk_o : OUT std_logic;
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m_core_n_clk_o : OUT std_logic;
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m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0);
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s_spi_miso_o : OUT std_logic;
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s_di_req_o : OUT std_logic;
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s_do_valid_o : OUT std_logic;
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s_do_o : OUT std_logic_vector(31 downto 0);
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s_do_transfer_o : OUT std_logic;
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s_wren_o : OUT std_logic;
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s_wren_ack_o : OUT std_logic;
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s_rx_bit_reg_o : OUT std_logic;
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s_state_dbg_o : OUT std_logic_vector(5 downto 0)
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);
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END COMPONENT;
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--=========================================================
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-- constants
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--=========================================================
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constant fifo_memory_size : integer := 16;
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--=========================================================
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-- types
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--=========================================================
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type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0);
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--=========================================================
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-- signals to connect the instances
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--=========================================================
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-- internal clk and rst
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signal m_clk : std_logic := '0'; -- clock domain for the master parallel interface. Must be faster than spi bus sck.
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signal s_clk : std_logic := '0'; -- clock domain for the slave parallel interface. Must be faster than spi bus sck.
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signal rst : std_logic := 'U';
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-- spi bus wires
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signal spi_sck : std_logic;
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signal spi_ssel : std_logic;
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signal spi_miso : std_logic;
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signal spi_mosi : std_logic;
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-- master parallel interface
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signal di_m : std_logic_vector (N-1 downto 0) := (others => '0');
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signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U');
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signal do_valid_m : std_logic;
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signal do_transfer_m : std_logic;
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signal di_req_m : std_logic;
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signal wren_m : std_logic := '0';
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signal wren_o_m : std_logic := 'U';
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signal wren_ack_o_m : std_logic := 'U';
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signal rx_bit_reg_m : std_logic;
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signal state_m : std_logic_vector (5 downto 0);
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signal core_clk_o_m : std_logic;
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signal core_n_clk_o_m : std_logic;
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signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
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-- slave parallel interface
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signal di_s : std_logic_vector (N-1 downto 0) := (others => '0');
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signal do_s : std_logic_vector (N-1 downto 0);
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signal do_valid_s : std_logic;
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signal do_transfer_s : std_logic;
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signal di_req_s : std_logic;
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signal wren_s : std_logic := '0';
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signal wren_o_s : std_logic := 'U';
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signal wren_ack_o_s : std_logic := 'U';
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signal rx_bit_reg_s : std_logic;
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signal state_s : std_logic_vector (5 downto 0);
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-- signal sh_reg_s : std_logic_vector (N-1 downto 0);
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--=========================================================
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-- Clock period definitions
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--=========================================================
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constant m_clk_period : time := 10 ns; -- 100MHz master parallel clock
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constant s_clk_period : time := 10 ns; -- 100MHz slave parallel clock
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BEGIN
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--=========================================================
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-- Component instantiation for the Unit Under Test (UUT)
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--=========================================================
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Inst_spi_loopback: spi_loopback
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port map(
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----------------MASTER-----------------------
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m_clk_i => m_clk,
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m_rst_i => rst,
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m_spi_ssel_o => spi_ssel,
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m_spi_sck_o => spi_sck,
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m_spi_mosi_o => spi_mosi,
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m_spi_miso_i => spi_miso,
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m_di_req_o => di_req_m,
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m_di_i => di_m,
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m_wren_i => wren_m,
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m_do_valid_o => do_valid_m,
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m_do_o => do_m,
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----- debug -----
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m_do_transfer_o => do_transfer_m,
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m_wren_o => wren_o_m,
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m_wren_ack_o => wren_ack_o_m,
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m_rx_bit_reg_o => rx_bit_reg_m,
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m_state_dbg_o => state_m,
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m_core_clk_o => core_clk_o_m,
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m_core_n_clk_o => core_n_clk_o_m,
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m_sh_reg_dbg_o => sh_reg_m,
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----------------SLAVE-----------------------
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s_clk_i => s_clk,
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s_spi_ssel_i => spi_ssel,
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s_spi_sck_i => spi_sck,
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s_spi_mosi_i => spi_mosi,
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s_spi_miso_o => spi_miso,
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s_di_req_o => di_req_s,
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s_di_i => di_s,
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s_wren_i => wren_s,
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s_do_valid_o => do_valid_s,
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s_do_o => do_s,
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----- debug -----
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s_do_transfer_o => do_transfer_s,
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s_wren_o => wren_o_s,
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s_wren_ack_o => wren_ack_o_s,
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s_rx_bit_reg_o => rx_bit_reg_s,
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s_state_dbg_o => state_s
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-- s_sh_reg_dbg_o => sh_reg_s
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);
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--=========================================================
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-- Clock generator processes
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--=========================================================
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m_clk_process : process
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begin
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m_clk <= '0';
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wait for m_clk_period/2;
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m_clk <= '1';
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wait for m_clk_period/2;
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end process m_clk_process;
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s_clk_process : process
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begin
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s_clk <= '0';
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wait for s_clk_period/2;
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s_clk <= '1';
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wait for s_clk_period/2;
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end process s_clk_process;
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--=========================================================
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-- rst_i process
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--=========================================================
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rst <= '0', '1' after 20 ns, '0' after 100 ns;
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--=========================================================
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-- Master interface process
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--=========================================================
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master_tx_fifo_proc: process is
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variable fifo_memory : fifo_memory_type :=
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(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
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X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
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variable fifo_head : integer range 0 to fifo_memory_size-1;
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begin
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-- synchronous rst_i
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wait until rst = '1';
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wait until m_clk'event and m_clk = '1';
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di_m <= (others => '0');
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wren_m <= '0';
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fifo_head := 0;
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wait until rst = '0';
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wait until di_req_m = '1'; -- wait shift register request for data
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-- load next fifo contents into shift register
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for cnt in 0 to (fifo_memory_size/2)-1 loop
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fifo_head := cnt; -- pre-compute next pointer
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wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
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di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
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wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
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wren_m <= '1'; -- write data into spi master
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wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
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wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
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wren_m <= '0'; -- remove write enable signal
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wait until di_req_m = '1'; -- wait shift register request for data
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end loop;
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wait until spi_ssel = '1';
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wait for 2000 ns;
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for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop
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fifo_head := cnt; -- pre-compute next pointer
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wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
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di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
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wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
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wren_m <= '1'; -- write data into spi master
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wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
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wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
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wren_m <= '0'; -- remove write enable signal
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wait until di_req_m = '1'; -- wait shift register request for data
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end loop;
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wait;
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end process master_tx_fifo_proc;
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--=========================================================
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-- Slave interface process
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--=========================================================
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slave_tx_fifo_proc: process is
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variable fifo_memory : fifo_memory_type :=
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(X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394",
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X"be575ec5",X"2fa57410",X"cafed0ce",X"afadab0a",X"bac7ed1a",X"f05fac75",X"2acbac7e",X"12345678");
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variable fifo_head : integer range 0 to fifo_memory_size-1;
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begin
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-- synchronous rst_i
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wait until rst = '1';
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wait until s_clk'event and s_clk = '1';
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di_s <= (others => '0');
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wren_s <= '0';
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fifo_head := 0;
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wait until rst = '0';
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wait until di_req_s = '1'; -- wait shift register request for data
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-- load next fifo contents into shift register
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for cnt in 0 to fifo_memory_size-1 loop
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fifo_head := cnt; -- pre-compute next pointer
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wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
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di_s <= fifo_memory(fifo_head); -- place data into tx_data input bus
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wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
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wren_s <= '1'; -- write data into shift register
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wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
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wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
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wren_s <= '0'; -- remove write enable signal
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wait until di_req_s = '1'; -- wait shift register request for data
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end loop;
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wait;
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end process slave_tx_fifo_proc;
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END ARCHITECTURE behavior;
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